Error Interrupt Status (errorintrsts) – Offset 32 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Error Interrupt Status (errorintrsts) – Offset 32

Bit Range	Default	Access	Field Name and Description
14:13	-	-	Reserved
12	0h	RW/1C	Target Response error (target_response_error) Occurs when detecting ERROR in DMA transaction. 0 - no error 1 – error
11:10	-	-	Reserved
9	0h	RW/1C	ADMA Error (adma_error) This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register. 1- Error 0 -No error
8	0h	RW/1C	Auto CMD Error (auto_cmd_err_sd_mode) This bit is set when detecting that one of the bits D00-D04 in Auto CMD Error Status register has changed from 0 to 1. In case of Auto CMD12, this bit is set to 1, not only when the errors in Auto CMD12 occur but also when Auto CMD12 is not executed due to the previous command error. 0 - No Error 1 – Error
7	0h	RW/1C	Current Limit Error (current_limit_err) By setting the SD Bus Power bit in the Power Control Register, the HC is requested to supply power for the SD Bus. If the HC supports the Current Limit Function, it can be protected from an Illegal card by stopping power supply to the card in which case this bit indicates a failure status. Reading 1 means the HC is not supplying power to SD card due to some failure. Reading 0 means that the HC is supplying power and no error has occurred. This bit shall always set to be 0, if the HC does not support this function. 0 - No Error 1 - Power Fail
6	0h	RW/1C	Data End Bit Error (data_end_bit_err) Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status. 0 - No Error 1 – Error
5	0h	RW/1C	Data CRC Error (data_crc_err_sd_mode) Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 010b. 0 - No Error 1 – Error
4	0h	RW/1C	Data Timeout Error (data_timeout_err_sd_mode) Occurs when detecting one of following timeout conditions:{br]1. Busy Timeout for R1b, R5b type. 2. Busy Timeout after Write CRC status 3. Write CRC status Timeout 4. Read Data Timeout 0 - No Error 1 – Timeout
3	0h	RW/1C	Command Index Error (cmd_index_err_sd_mode) Occurs if a Command Index error occurs in the Command Response. 0 - No Error 1 – Error
2	0h	RW/1C	Command End Bit Error (cmd_end_bit_err_sd_mode) Occurs when detecting that the end bit of a command response is 0. 0 - No Error 1 - End Bit Error Generated
1	0h	RW/1C	Command CRC Error (cmd_crc_err_sd_mode) Command CRC Error is generated in two cases. 1. If a response is returned and the Command Time-out Error is set to 0, this bit is set to 1 when detecting a CRT error in the command response 2. The HC detects a CMD line conflict by monitoring the CMD line when a command is issued. If the HC drives the CMD line to 1 level, but detects 0 level on the CMD line at the next SDCLK edge, then the HC shall abort the command (Stop driving CMD line) and set this bit to 3. The Command Timeout Error shall also be set to 1 to distinguish CMD line conflict. 0 - No Error 1 - CRC Error Generated
0	0h	RW/1C	Command Timeout Error (cmd_timeout_err_sd_mode) Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict, in which case Command CRC Error shall also be set. This bit shall be set without waiting for 64 SDCLK cycles because the command will be aborted by the HC. 0 - No Error 1 – Timeout