Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Global Control (GCTL) – Offset 8
CRSTB bit is not affected by controller reset.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:9 | - | - | Reserved
|
8 | 0b | RW | Accept Unsolicited Response Enable (UNSOL) If UNSOL is a 1, Unsolicited Responses from the codecs are accepted by the controller |
7:2 | - | - | Reserved
|
1 | 0b | RW/1S/V | Flush Control (FCNTRL) Writing a 1 to this bit initiates a flush. When the flush completion is received by the controller, hardware sets the Flush Status bit and clears this Flush Control bit. |
0 | 0b | RW/V | Controller Reset# (CRSTB) After the hardware has completed sequencing into the reset state, it will report a 0 in this bit. Software must read a 0 from this bit to verify that the controller is in reset. Writing a 1 to this bit causes the controller to exit its reset state and deassert the Intel HD Audio link RESET# signal. Software is responsible for setting/clearing this bit such that the minimum Intel HD Audio link RESET# signal assertion pulse width specification is met. When the controller hardware is ready to begin operation, it will report a 1 in this bit. Software must read a 1 from this bit before accessing any controller registers. The CRST bit defaults to a 0 after hardware reset, therefore software needs to write a 1 to this bit to begin operation. Note that the CORB/RIRB RUN bits and all Stream RUN bits must be verified cleared to zero before CRST bit is written to 0 (asserted) in order to assure a clean re-start. When setting or clearing CRST, software must ensure that minimum link timing requirements (minimum RESET# assertion time, etc.) are met. When CRST is 0 indicating that the controller is in reset, writes to all Intel HD Audio memory mapped registers are ignored as if the device is not present. The only exception is the Global Control register containing the CRST bit itself. The Global Control register is write-able as a DWord, Word, or Byte even when CRST is 0 if the byte enable for the byte containing the CRST bit (Byte Enable 0) is active. If Byte Enable 0 is not active, writes to the Global Control register will be ignored when CRST is 0. When CRST is 0, reads to Intel HD Audio memory mapped registers will return their default value except for registers that are not reset with PLTRST# or on a D3hot to D0 transition. |