Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Gigabit Ethernet Capabilities and Status (GBECSR_20) – Offset 20
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0x0 | RW/V | Wait () Set to 1 by the Gigabit Ethernet Controller to indicate that a PCI Express* to SMBus transition is taking place. The ME/Host should not issue new MDIC transactions while this bit is set to 1. This bit is auto cleared by hardware after the transition has occurred. |
30 | 0x0 | RW/V | Error () Set to 1 by the Gigabit Ethernet Controller when it fails to complete an MDI read.Software should make sure this bit is clear before making an MDI read or write command. |
29 | 0x0 | RW/V | Interrupt Enable (IE) When set to 1 by software, it will causean Interrupt to be asserted to indicate the end of an MDI cycle. |
28 | 0x1 | RW/V | Ready Bit (RB) Set to 1 by the Gigabit Ethernet Controller at the end of the MDItransaction. This bit should be reset to 0 by software at the same time the command is written. |
27:26 | 0x0 | RW/V | MDI Type () [br[ |
25:21 | 0x0 | RW/V | LAN Connected Device Address (PHYADD)
|
20:16 | 0x0 | RW/V | LAN Connected Device Register Address (REGADD)
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15:0 | 0x0 | RW/V | DATA () In a Write command, software places the data bits and the MAC shifts them out to the LAN Connected Device. In a Read command, the MAC reads these bits serially from theLAN Connected Device and software can read them from this location. |