Root Error Command (REC) – Offset 20ac - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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Root Error Command (REC) – Offset 20ac

Offset 20ACh: REC Root Error Command

In an exposed AER capability, this register allows errors to generate interrupts. For this implementation, and for RCRBs in general, interrupts cannot be generated, so this register is reserved.

Bit Range	Default	Access	Field Name and Description
31	0b	RW	Drop Poisoned Downstream Packets (DPDP) When set to a '1': if downstream packet on OPI is received with the EP bit set, this packet and all subsquent packets with data received on DMI for any VC will have their Unsupported Transaction (UT) field set causing them to be forwarded to the Error Handler. When cleared to a '0', downstream packets from OPI with the EP bit set are forwarded onto the downstream backbone normally.
30	0b	RW	Unsupported Transaction Policy Bit (UTPB) When set to 1, the Unsupported Transactions detected on OPI will not set the UES.URE bit. This subsequently ensures that SERR will never be signaled in response to Unsupported Transactions regardless of UEV.URE. When set to 0, the Unsupported Transactions detected on OPI will set the UES.URE bit.
29:0	-	-	Reserved

Bit Range

Default

Access

Field Name and Description

Drop Poisoned Downstream Packets (DPDP)

When set to a '1': if downstream packet on OPI is received with the EP bit set, this packet and all subsquent packets with data received on DMI for any VC will have their Unsupported Transaction (UT) field set causing them to be forwarded to the Error Handler.

When cleared to a '0', downstream packets from OPI with the EP bit set are forwarded onto the downstream backbone normally.

Unsupported Transaction Policy Bit (UTPB)

When set to 1, the Unsupported Transactions detected on OPI will not set the UES.URE bit. This subsequently ensures that SERR will never be signaled in response to Unsupported Transactions regardless of UEV.URE.

When set to 0, the Unsupported Transactions detected on OPI will set the UES.URE bit.

29:0

Reserved

Root Error Status (RES)

Correctable Error Mask (CEM) Root Error Status (RES)