Power Management Data, Control/Status Register Bridge Support Extensions, Control And Status (KT_HOST_PMD_PMCSRBSE_PMCSR) – Offset 54 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Power Management Data, Control/Status Register Bridge Support Extensions, Control And Status (KT_HOST_PMD_PMCSRBSE_PMCSR) – Offset 54

This register contains the power management data, control and status register bridge support extensions, control and status registers.

Bit Range	Default	Access	Field Name and Description
31:24	00h	RO	Data (Data) Not implemented. Hardwired to 0.
23:16	00h	RO	Control/Status Register Bridge Support Extensions (CSRBSE) Not implemented. Hardwired to 0.
15	0b	RO	PME Status (PMESTS) This bit is set when the function would normally assert the PME signal independent of the state of the PME_En bit. Writing a 1 to this bit will clear it and cause the function to stop asserting a PME (if enabled). Writing a 0 has no effect. If the function supports PME from D3cold, then this bit is sticky and must be explicitly cleared by the operating system each time the operating system is initially loaded. Not implemented. Hardwired to 0.
14:13	00b	RO	Data Scale (DS) Not implemented. Hardwired to 0.
12:9	0000b	RO	Data Select (DSEL) Not implemented. Hardwired to 0.
8	0b	RO	PME Enable (PMEEN) A 1 enables the function to assert PME. When 0, PME assertion is disabled. This bit defaults to 0 if the function does not support PME generation from D3cold. If the function supports PME from D3cold then this bit is sticky and must be explicitly cleared by the operating system each time it is initially loaded. Not implemented. Hardwired to 0.
7:4	-	-	Reserved
3	1b	RO	No Soft Reset (NSR) When set to 1, this bit indicates that devices transitioning from D3hot to D0 because of PowerState commands do not perform an internal reset. Configuration Context is preserved. Upon transition from the D3hot to the D0 Initialized state, no additional operating system intervention is required to preserve Configuration Context beyond writing the PowerState bits.
2	-	-	Reserved
1:0	00b	RW	Power State (PWRST) This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below: 00b - D0 01b - D1 10b - D2 11b - D3hot If software attempts to write an unsupported, optional state to this field, the write operation must complete normally on the bus; however, the data is discarded and no state change occurs.