Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
NMI Status (GPI_NMI_STS_GPP_D_0) – Offset 1c0
Register bits in this register are implemented for GPP_D signals that have NMI capability only. Other bits are reserved and RO.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:5 | - | - | Reserved
|
4 | 0b | RW/1C | GPI NMI Status (GPI_NMI_STS_GPPC_D_4) Same description as bit 0. |
3 | 0b | RW/1C | GPI NMI Status (GPI_NMI_STS_GPPC_D_3) Same description as bit 0. |
2 | 0b | RW/1C | GPI NMI Status (GPI_NMI_STS_GPPC_D_2) Same description as bit 0. |
1 | 0b | RW/1C | GPI NMI Status (GPI_NMI_STS_GPPC_D_1) Same description as bit 0. |
0 | 0b | RW/1C | GPI NMI Status (GPI_NMI_STS_GPPC_D_0) This bit is set to 1 by hardware when an edge event is detected (SeeRxEdCfg, RxInv) on pad and all the following conditions are true: |