Debug Capability Port Status and Control Register (DCPORTSC) – Offset 8728 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Debug Capability Port Status and Control Register (DCPORTSC) – Offset 8728

Bit Range	Default	Access	Field Name and Description
30:24	-	-	Reserved
23	0b	RW/1C	Port Config Error Change (CEC) This flag indicates that the port failed to configure its link partner. 0 = No change. 1 = Port Config Error detected. Software shall clear this bit by writing a '1' to it.
22	0b	RW/1C	Port Link Status Change (PLC) Port Link Status Change (PLC) = RW1C. Default = ‘0’. This flag is set to ‘1’ due to thefollowing PLS transitions:<br>Transition Condition<br>U0 -> U3 Suspend signaling detected from Debug Host<br>U3 -> U0 Resume completePolling -> Disabled Training Error<br>Ux or Recovery -> Inactive Error<br>Software shall clear this bit by writing a '1' to it.<br>This field is ‘0’ if DCE is ‘0’.
21	0b	RW/1C	Port Reset Change (PRC) This bit is set when reset processing on this port is complete (i.e. a '1' to '0' transition of PR). '0' = No change. '1' = Reset complete.Software shall clear this bit by writing a '1' to it. This field is '0' if DCE is '0'.
20:18	-	-	Reserved
17	0b	RW/1C	Connect Status Change (CSC) an already-set bit (i.e., the bit will remain '1'). Software shall clear this bit by writing a '1' to it. This field is '0' if DCE is '0'.
16:14	-	-	Reserved
13:10	0h	RO	Port Speed (PSPD) Port Speed (Port Speed) – RO. Default = ‘0’. This field identifies the speed of the port. Thisfield is only relevant when a Debug Host is attached (CCS = ‘1’) in all other cases this field shallindicate Undefined Speed.<br>Value Speed 0100b SuperSpeed (5Gb/s) All other values reserved.
9	-	-	Reserved
8:5	4h	RO	Port Link State (PLS) Port Link State (PLS) – RO. Default = undefined. This field reflects its current link state. Thisfield is only relevant when a Debug Host is attached (Debug Port Number > ‘0’).<br> 0: Link is in the U0 State <br>1: Link is in the U1 State<br>2: Link is in the U2 State<br>3: Link is in the U3 State (Device Suspended)<br>4: Link is in the Disabled State<br>5: Link is in the RxDetect State<br>6: Link is in the Inactive State<br>7: Link is in the Polling State<br>8: Link is in the Recovery State<br>9: Link is in the Hot Reset State<br>15-10: Reserved<br>Note: Transitions between different states are not reflected until the transition is complete
4	0b	RO	Port Reset (PR) '1' = Port is in Reset. '0' = Port is not in Reset. This bit is set to '1' when the bus reset sequence as defined in the USB Specification is detected on the Root Hub port assigned to the Debug capability. It is cleared when the bus reset sequence is completed by the Debug Host, and the DbC shall transition to the USB Default state. A '0' to '1' transition of this bit shall clear DCPORTSC PED ('0'). This field is '0' if DCE or CCS are '0'.
3:2	-	-	Reserved
1	0b	RW	Port Enabled/Disabled (PED) Port Enabled/Disabled (PED) – RW. Default = ‘0’. ‘1’ = Enabled. ‘0’ = Disabled. This flag shallbe set to '1' by a '0' to '1' transition of CCS or a '1' to '0' transition of the PR. When PEDtransitions from '1' to '0' due to the assertion of PR, the port's link shall transition to theRx.Detect state. This flag may be used by software to enable or disable the operation of theRoot Hub port assigned to the Debug Capability. The Debug Capability Root Hub portoperation may be disabled by a fault condition (disconnect event or other fault condition, e.g. aLTSSM Polling substate timeout, tPortConfiguration timeout error, etc.), the assertion ofDCPORTSC PR, or by software.<br> 0 = Debug Capability Root Hub port is disabled.<br> 1 = Debug Capability Root Hub port is enabled.<br> When the port is disabled (PED = ‘0’) the port’s link shall enter the SS.Disabled state andremain there until PED is reasserted ('1') or DCE is negated ('0'). Note that the Root Hub port isremains mapped to Debug Capability while PED = '0'. While PED = '0' the Debug Capability willappear to be disconnected to the Debug Host.<br> This field is ‘0’ if DCE or CCS are ‘0’.
0	0b	RO	Current Connect Status (CCS) '1' = A Root Hub port is connected to a Debug Host and assigned to the Debug Capability. '0' = No Debug Host is present. This value reflects the current state of the port, and may not correspond to the value reported by the Connect Status Change (CSC) field in the Port Status Change Event that was generated by a '0' to '1' transition of this bit. This flag is '0' if Debug Capability Enable (DCE) is '0'.