Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Timeout Control (timeoutcontrol) – Offset 2e
This value determines the interval by which DAT linetime-outs are detected.Refer to the Data Time-out Error in the Error InterruptStatus register for information on factors that dictatetime-out generation. Time-out clock frequency will begenerated by dividing the sd clock TMCLK by this value.When setting this register, prevent inadvertenttime-out events by clearing the Data Time-out ErrorStatus Enable (in the Error Interrupt Status Enableregister)
1110 - TMCLK * 2^27
0001 - TMCLK * 2^14
0000 - TMCLK * 2^13.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
6:4 | - | - | Reserved
|
3:0 | 0h | RW | Data Timeout Counter Value (timeout_ctrvalue) This value determines the interval by which DAT line time-outs are detected. |