Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
PM_SYNC Miscellaneous Configuration (PM_SYNC_MISC_CFG) – Offset 18c8
This register is used to configure miscellaneous aspects of the PM_SYNC pin.
This register is in the CORE power well and is reset by PLTRST#.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:16 | - | - | Reserved
|
15 | 0b | RW/L | PM_SYNC Configuration Lock (PM_SYNC_LOCK) The bit is used to lock down the settings of several PM_SYNC-related configuration bits. This bit is self-locking (i.e. once written to '1', it can only be cleared by PLTRST#). |
14:12 | - | - | Reserved
|
11 | 0b | RW/L | GPIO_D Pin Selection (GPIO_D_SEL) There are two possible GPIOs that can be routed to the GPIO_D PM_SYNC state. This bit selects between them: |
10 | 0b | RW/L | GPIO_C Pin Selection (GPIO_C_SEL) There are two possible GPIOs that can be routed to the GPIO_C PM_SYNC state. This bit selects between them: |
9 | 0b | RW/L | GPIO_B Pin Selection (GPIO_B_SEL) There are two possible GPIOs that can be routed to the GPIO_B PM_SYNC state. This bit selects between them: |
8 | 0b | RW/L | GPIO_A Pin Selection (GPIO_A_SEL) There are two possible GPIOs that can be routed to the GPIO_A PM_SYNC state. This bit selects between them: |
7:0 | - | - | Reserved
|