Status and Command (STATUSCOMMAND) – Offset 4 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Introduction
8254 Timer
Advanced Programmable Interrupt Controller (APIC)
APIC Indirect
CNVi PCI Configuration
DCI PCR
- DCI Control (ECTRL)
EMMC Additional
EMMC Memory Mapped
EMMC PCI Configuration
eMMC PCR
- Dynamic Clock Gating Control (GPPRVRW1)
Enhanced SPI (eSPI) PCI Configuration
eSPI PCR
FIA Configuration PCR
GbE Configuration
GbE Memory Mapped I/O
Generic SPI (GSPI) Additional
Generic SPI (GSPI) DMA Controller
Generic SPI (GSPI) Memory Mapped
GPIO Community 0
GPIO Community 1
GPIO Community 2
GPIO Community 3
GPIO Community 4
GSPI PCI Configuration
High Definition Audio (D31:F3) Memory Mapped I/O
High Definition Audio (D31:F3) PCI Configuration
HPET Memory Mapped
I2C Additional
I2C DMA Controller
I2C Memory Mapped
I2C PCI Congifuration
IDE Redirect PCI Configuration (D22:F2)
Integrated Clock (ICC) Configuration
- CMU_ONE_DWORD25 (cmu_one_dword25)
Intel RST for PCIe Storage (Remapping) PCI Configuration (D24:F0)
Intel RST for PCIe Storage MMIO
Intel(R) Management Engine Interface PCI Configuration
Intel(R) MEI MMIO
- DEVIDLE Control (HECI1_DEVIDLEC)
Intel(R) Trace Hub Configuration
Intel® HD Audio PCR
- Function Configuration (FNCFG)
Interrupt
Interrupt PCR
IO Trap
ISH
ISH PCH Configuration
ISH PCR
- Power Management Control (PMCTL)
Keyboard and Text (KT) Additional Configuration
- Power Management Control and Status (KT_CSXE_PMD_PMCSRBSE_PMCSR)
Keyboard and Text (KT) PCI Configuration (D22:F3)
LPC Configuration
LPC PCR
- General Control And Function Disable (GCFD)
OPI PCR
P2SB PCI Configuration
PCI Express* Port Configuration
PMC I/O Based
PMC Memory Mapped
PMC SSRAM PCI Configuration
Power Management Configuration
Processor Interface Memory
PSF1
PSF2
PSF3
PSF4
PSF5
RTC Indexed
RTC PCR
SATA ABAR
SATA AIDP
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Configuration
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
SATA MXTBA
SDXC (SD Card) PCR
- Dynamic Clock Gating Control (GPPRVRW1)
SDXC Additional Memory Mapped
SDXC Memory Mapped
SDXC PCI Configuration
SMBus Configuration
SMBus I/O and Memory Mapped I/O
SMBus PCR
SMBus TCO I/O
SPI Configuration
SPI Memory Mapped
Thermal Reporting Configuration
Thermal Reporting Memory Mapped
UART Additional Memory Mapped
UART DMA Controller
UART Memory Mapped
UART PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration
xHCI Configuration
xHCI Memory Mapped

Status and Command (STATUSCOMMAND) – Offset 4

Bit Range	Default	Access	Field Name and Description
30	-	-	Reserved
29	0h	RW/1C	Received Master Abort (RMA) If the completion status received from IOSF is UR, the Bridge sets this bit. Thesoftware writes a 1 to this bit to clear it.
28	0h	RW/1C	Received Target Abort (RTA) If the completion status received from IOSF is CA, the Bridge sets this bit. Thesoftware writes a 1 to this bit to clear it.
27:21	-	-	Reserved
20	1h	RO	Capabilities List (CAPLIST) Indicates that the controller contains a capabilities pointer list. The firstitem is pointed to by looking at the configuration offset 34h.
19	0h	RO	Interrupt Status (INTR_STATUS) This bit reflects state of interrupt in the device Only when theInterrupt Disable bit in the command register is a 0 and this Interrupt Status bit is a1, is the device/function interrupt message sent. Setting the Interrupt Disable bit to a1 has no effect on the state of this bit. This bit reflects Legacy interrupt status.
18:11	-	-	Reserved
10	0h	RW	Interrupt Disable (INTR_DISABLE) Interrupt Disable: Setting this bit disables INTx assertion fromBridge. The interrupt disabled is legacy INTx# interrupt, which is the Bridge does notsend Interrupt Assert message through the IOSF Sideband Channel. Reset value ofthis bit is 0. This bit has no connection with the interrupt status bit.
9	-	-	Reserved
8	0h	RW	SERR Enable (SERR_ENABLE) Not implemented
7:3	-	-	Reserved
2	0h	RW	Bus Master Enable (BME) Bus Master Enable: If this bit is 0,the Bridge does not generate any newupstream transaction on IOSF as a master. Reset value of this bit is 0.
1	0h	RW	Memory Space Enable (MSE) Memory Space Enable: This bit controls Bridge response to downstreammemory accesses. When set, accesses to memory space of the device is enabled.Reset value of this bit is 0.
0	-	-	Reserved

Base Address Register (BAR)

Device ID and Vendor ID (DEVVENDID) Base Address Register (BAR)