SMI Status Register (SMI_STS) – Offset 34 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

SMI Status Register (SMI_STS) – Offset 34

Lockable: No

Usage: ACPI or Legacy

Power Well: Primary

Note: If the corresponding _EN bit is set when the _STS bit is set, the Intel PCH will cause an SMI# (except bits 8-10, which don't cause SMI#)

Bit Range	Default	Access	Field Name and Description
31	0b	RO/V	XHCI SMI Status (XHCI_SMI_STS) This bit will be set when any USB3 (XHCI) Host Controller is requesting an SMI.
30	0b	RO/V	ME SMI Status (ME_SMI_STS) This bit will be set when ME is requesting an SMI#.
29	0b	RW/1C/V	Intel Serial I/O SMI Status (LPSS_SMI_STS) This bit gets set when Intel Serial I/O agent is requesting SMI #. This bit is set by hardware and cleared by software writing a 1 to this bit position.
28	0b	RO/V	eSPI SMI Status (ESPI_SMI_STS) This bit is set if an eSPI agent is requesting an SMI#. This bit is set by hardware and cleared when the PCH receives an eSPI SMI deassertion from an eSPI device.
27	0b	RW/1C/V	GPIO Unlock SMI Status (GPIO_UNLOCK_SMI_STS) This bit will be set of the GPIO registers lockdown logic is requesting an SMI#. Writing a '1' to this bit position clears this bit to '0'. This bit is reset by PLTRST# assertion.
26	0b	RO/V	SPI SMI Status (SPI_SMI_STS) This bit will be set when the SPI logic is requesting an SMI#. This bit is read only because the sticky status and enable bits associated with this function are located in the SPI registers.
25	0b	RW/1C/V	SCC SMI Status (SDX_SMI_STS) This bit gets set when SCC agent is requesting SMI#.This bit is set by hardware and cleared by software writing a 1 to this bit position
24:22	-	-	Reserved
21	0b	RO/V	Monitor Status (MONITOR_STS) This bit will be set if the Trap/SMI logic has caused the SMI. This will occur when the CPU or a bus master accesses an assigned register (or a sequence of accesses).
20	0b	RO/V	PCI_EXP_SMI Status (PCI_EXP_SMI_STS) 1- PCI Express SMI event occurred. This could be due to a PCI Express PME event or Hot Plug Event.
19:17	-	-	Reserved
16	0b	RW/1C/V	SMBus SMI Status (SMBUS_SMI_STS) 0 = This bit is set from the 64 KHz clock domain used by the SMBus. Software must wait at least 15.63 microseconds after initial assertion of this bit before clearing it. This bit is sticky and is cleared by writing a 1 to this bit position. 1 = Indicates that the SMI# was caused by: 1.The SMBus Slave receiving a message that an SMI# should be caused, or 2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the SMBALERT_DIS bit is cleared, or 3. The SMBus Slave receiving a HOST_NOTIFY message and the HOST_NOTIFY_INTREN and the SMB_SMI_EN bits are set, or 4. The SMBus Slave receiving a "SMI in S0" message. This bit is reset by PLTRST# assertion.
15	0b	RO/V	SERIRQ_SMI Status (SERIRQ_SMI_STS) 1 = Indicates the SMI# was caused by the SERIRQ decoder. 0 = SMI# not caused by SERIRQ decoder. NOTE: this bit is not sticky. Writes to this bit will have no effect.
14	0b	RW/1C/V	Periodic Status (PERIODIC_STS) This bit will be set at the rate determined by the PER_SMI_SEL bits. If the PERIODIC_EN bit is also set, the Intel PCH will generate an SMI#. This bit is cleared by writing a 1 to this bit position. This bit is reset by PLTRST# assertion.
13	0b	RW/1C/V	TCO Status (TCO_STS) 0 = SMI not caused by TCO logic. 1 = Indicates SMI was caused by the TCO logic. NOTE: Will not cause wake event. This bit is cleared by writing a 1 to this bit position. This bit is reset by PLTRST# assertion.
12	0b	RO/V	DEVMON Status (DEVMON_STS) This read-only bit is set when bit 0 in the DEVTRAP_STS register is set. It is not sticky, so writes to this bit will have no effect.
11	0b	RW/1C/V	Microcontroller SMI Status (MCSMI_STS) This bit is set if there is an access to the power management microcontroller range (62h or 66h). If this bit is set, and the MCSMI_EN bit is also set, the Intel PCH will generate an SMI#. This bit is set by hardware and cleared by software writing a 1 to its bit position. This bit is reset by PLTRST# assertion.
10	0b	RO/V	GPIO SMI Status (GPIO_SMI_STS) This bit will be a 1 if any GPIO that is enabled to trigger SMI is asserted. GPIOs that are not routed to cause an SMI will have no effect on this bit. This bit is NOT sticky. Writes to this bit will have no effect. Note: See the GPIO chapter for the individual GPIO SMI status, enable, and routing bit definitions.
9	0b	RO/V	GPE0 Status (GPE0_STS) There are several status/enable bit pairs in GPE0_STS/EN_127_96 that are capable of triggering SMI#s. This bit is a logical OR of all of those pairs (i.e. this bit is asserted whenever at least one of those pairs has both the status and enable bit asserted). This bit is NOT sticky. Writes to this bit will have no effect. Note: The setting of this bit does not cause the SMI#. The following bit pairs are included in this logical OR: - GPE0_STS/EN_127_96 [18, 17, 16, 13, 11, 10, 8, 2]
8	0b	RO/V	PM1 Status Register (PM1_STS_REG) This is an OR of the bits (except for bits 5 and 4) in the ACPI PM1 Status Reg. Not sticky. Writes to this bit have no effect. Note: The setting of this bit does not cause the SMI#.
7	-	-	Reserved
6	0b	RW/1C/V	Software SMI Timer Status (SWSMI_TMR_STS) This bit will be set to 1 by the hardware when the Software SMI# Timer expires. This bit will remain 1 until the software writes a 1 to this bit. This bit is reset by PLTRST# assertion.
5	0b	RW/1C/V	APM Status (APM_STS) SMI# was generated by a write access to the APM control register and if the APMC_EN bit is set. This bit is cleared by writing a one to its bit position. This bit is reset by PLTRST# assertion.
4	0b	RW/1C/V	SMI_ON_SLP_EN Status (SMI_ON_SLP_EN_STS) This bit will be set by the Intel PCH when a write access attempts to set the SLP_EN bit. This bit is cleared by writing a 1 to this bit position. This bit is reset by PLTRST# assertion.
3	0b	RO/V	Legacy USB Status (LEGACY_USB_STS) This non-sticky read-only bit is a logical OR of each of the SMI status bits in the USB Legacy Keybd Register ANDed with the corresponding enable bits. This bit will not be active if the enable bits are not set. Writes to this bit will have no effect.
2	0b	RW/1C/V	BIOS Status (BIOS_STS) This bit gets set by hardware when a 1 is written by software to the GBL_RLS bit. When both BIOS_EN and the BIOS_STS bit are set, an SMI# will be generated. The BIOS_STS bit is cleared when software writes a 1 to this bit position. This bit is reset by PLTRST# assertion.
1:0	-	-	Reserved