Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Global Rx Threshold Control (GRXTHRCFG) – Offset c10c
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30 | - | - | Reserved
|
29 | 1h | RW | USB ReceivePacket Count Enable (USBRxPktCntSel) This field enables/disables theUSB reception multi-packet thresholding: n 0: The core can only start reception on theUSB when the RX FIFO has space for at least one packet. n 1: The core can only startreception on the USB when the RX FIFO has space for at least USBRxPktCnt amount ofpackets. This mode is only valid in the host mode. It is only used for SuperSpeed. |
28 | - | - | Reserved
|
27:24 | 4h | RW | USB Receive Packet Count (USBRxPktCnt) This field specifies space (in number ofpackets) that must be available in the RX FIFO before the core can start thecorresponding USB RX transaction (burst). This field is only valid when the USB ReceivePacket Count Enable field is set to one. The valid values are from 1 to 15. |
23:19 | 08h | RW | USB Maximum Rx Burst Size (USBMaxRxBurstSize) This field is only validwhen USBRxPktCntSel is one. This field specifies the Maximum Bulk IN burst the coreshould do. When the system bus is slower than the USB, RX FIFO can overrun during along burst. User can program a smaller value to this field to limit the RX burst size thatthe core can do. It only applies to SS Bulk, Isochronous, and Interrupt IN endpoints inthe host mode. Valid values are from 1 to 16. |
18:0 | - | - | Reserved
|