Receive Buffer Register (RBR) – Offset 0 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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Receive Buffer Register (RBR) – Offset 0

RBR mode is only available when LCR register, DLAB bit = 0.

Bit Range	Default	Access	Field Name and Description
30:8	-	-	Reserved
7:0	0h	RO	Receive Buffer (RBR) Data byte received on the serial input port in UART mode. The data in this register is valid only if the Data Ready (DR) bit in the Line Status Register (LCR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an over-run error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO is preserved, but any incoming data are lost and an over-run error occurs.

Bit Range

Default

Access

Field Name and Description

30:8

Reserved

7:0

Receive Buffer (RBR)

Data byte received on the serial input port in UART mode. The data in this register is valid only if the Data Ready (DR) bit in the Line Status Register (LCR) is set.

If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an over-run error.

If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO is preserved, but any incoming data are lost and an over-run error occurs.

Transmit Holding Register (THR)

UART Memory Mapped Transmit Holding Register (THR)