PCI Clock Control (PCCTL) – Offset e0 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

PCI Clock Control (PCCTL) – Offset e0

PCI Clock Control.

Bit Range	Default	Access	Field Name and Description
30:10	-	-	Reserved
9	0b	RO/V	CLKRUN# Buffer Enable Override (CLKRUN_EN_OVR) When set to '1', SW is in control of the CLKRUN# buffer enable and the value in CLKRUN_EN_VAL will be propagated to the output buffer enable. When this bit is '0', HW will determine the value of the buffer enable.
8	0b	RO/V	CLKRUN# Override (CLKRUN_OVR) When set to '1', SW is in control of the CLKRUN# pin and the value in CLKRUN_VAL will be propagated to the output pin. When this bit is '0', HW will determine the value of the pin.
7	0b	RO/V	CLKRUN# Buffer Enable Value (CLKRUN_EN_VAL) Either HW or SW may own control of the CLKRUN# pin. This bit provides the value to drive on the active low CLKRUN# buffer enable if CLKRUN_EN_OVR is set to '1'.
6	0b	RO/V	CLKRUN# Pin Output Value (CLKRUN_VAL) Either HW or SW may own control of the CLKRUN# pin. This bit provides the value to drive on the pin if CLKRUN_OVR is set to '1'.
5	0b	RO/V	Stop PCI# Value (STP_PCI_VAL) Either Hardware or Software may own control of the internal STP_PCI#. This bit provides the value to drive on the STP_PCI# if STP_PCI_OVR is set to 1. Note: SW cannot control the STP_PCI# pin while PLTRST# is asserted (the pin will be at its reset default value).
4	0b	RO/V	Stop PCI# Override (STP_PCI_OVR) When set to 1, Firmware is in control of the STP_PCI# and the value in STP_PCI_VAL will be propagated to the internal STP_PCI#. When this bit is '0', HW will determine the value of the pin. Note:Bios cannot control the STP_PCI# pin while PLTRST# is asserted (the pin will be at its reset default value).
3:2	00b	RW	LPC Clock Valid Configuration (PCLKVLD_CFG) This field determines the relationship between the internally broadcast indication of the external LPC clock being valid vs. the STP_PCI# pin. Encodings: 00: 1 flop stage of delay from STP_PCI# (default) 01: No delay (edges match STP_PCI# 10: 2 flop stages of delay from STP_PCI# 11: Tie high (indicate that LPC clock is always valid)
1	-	-	Reserved
0	0b	RW	Clock Run Enable (CLKRUN_EN) Enables the CLKRUN# logic to stop the LPC clocks. If the SLP_EN bit is set, then the Intel PCH will drive CLKRUN# low. This will keep the LPC and LPC clocks running on the way to the sleeping state. This is required to meet an LPC specification. This does not necessarily mean that the CLKRUN_EN bit is forced low when SLP_EN is set. Even though the CLKRUN# signal will be low when SLP_EN is set, the state of the CLKRUN_EN bit is ignored when SLP_EN bit is set. This gives flexibility in the implementation.