Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_0) – Offset 600 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Pad Configuration DW0 (PAD_CFG_DW0_GPPC_A_0) – Offset 600

This register applies to GPP_A0.

Bit Range	Default	Access	Field Name and Description
31:30	01b	RW	Pad Reset Config (PADRSTCFG) This register controls which reset is used to reset GPIO pad register fields in PAD_CFG_DW0 and PAD_CFG_DW1 registers. This register can be used for Sx isolation of the associated signal if needed. 00 = RSMRST# 01 = Host deep reset. This reset occurs when any of the following occur: Host reset (with or without power cycle) is initiated, Global reset is initiated, or Deep Sx entry. This reset does NOT occur as part of S3/S4/S5 entry. 10 = PLTRST# 11 = Reserved
29	0b	RW	RX Pad State Select (RXPADSTSEL) Determines from which node the RX pad state for native function should be taken from. This field only affects the pad state value being fanned out to native function(s) and is not meaningful if the pad is in GPIO mode (i.e. Pad Mode = 0). 0 = Raw RX pad state directly from RX buffer 1 = Internal RX pad state (subject to RXINV and PreGfRXSel settings)
28	0b	RW	RX Raw Override to '1' (RXRAW1) This bit determines if the selected pad state is being overridden to '1'. This field is only applicable when the RX buffer is configured as an input in either GPIO Mode or native function mode. The override takes place at the internal pad state directly from buffer and before the RXINV. 0 = No Override 1 = RX drive 1 internally
27	-	-	Reserved
26:25	10b	RW	RX Level/Edge Configuration (RXEVCFG) Determines if the internal RX pad state (synchronized, filtered vs non-filtered version as determined by PreGfRXSel, and is further subject to RXInv) should be passed on to the next logic stage as is, as a pulse, or level signal. This field does not affect the received pad state (to GPIORXState or native functions) but how the interrupt or wake triggering events should be delivered to the GPIO Community Controller . 0h = Level 1h = Edge (RxInv=0 for rising edge; 1 for falling edge) 2h = Disable 3h = Either rising edge or falling edge
24	0b	RW	Pre Glitch Filter Stage RX Pad State Select (PREGFRXSEL) Determine if the synchronized version of the raw RX pad state should be subjected to glitch filter or not. This field only makes sense when the RX buffer is configured as an input and is not disabled. 0 = Select synchronized, non filtered RX pad state 1 = Select synchronized, filtered RX pad state The selected RX pad state can be further subjected to polarity inversion through RXINV
23	0b	RW	RX Invert (RXINV) This bit determines if the selected pad state should go through the polarity inversion stage. This field is only applicable when the RX buffer is configured as an input in either GPIO Mode or native function mode. The polarity inversion takes place at the mux node of raw vs filtered or non-filtered RX pad state, as determined by PreGfRXsel and RXPadStSel This bit does not affect GPIORXState. During host ownership GPIO Mode, when this bit is set to '1', then the RX pad state is inverted as it is sent to the GPIO-to-IOxAPIC, GPE/SCI, SMI, NMI logic or GPI_IS[n] that is using it. This is used to allow active-low and active-high inputs to cause IRQ, SMI#, SCI or NMI. 0 = No inversion 1 = Inversion
22:21	00b	RW	RX/TX Enable Config (RXTXENCFG) This controls the RX and TX buffer enablement for the function selected by Pad Mode. This field is not applicable in GPIO mode (PMode = 0. 0h = Function defined in Pad Mode controls TX and RX enablement 1h = Function controls TX enablement and RX is disabled with 0 being driven internally 2h = Function controls TX enablement and RX is disabled with 1 being driven internally 3h = Function controls TX enablement and RX is always enabled
20	0b	RW	GPIO Input Route IOxAPIC (GPIROUTIOXAPIC) Determines if the pad can be routed to cause peripheral IRQ when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0 = Routing does not cause peripheral IRQ 1 = Routing can cause peripheral IRQ Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the peripheral IRQ indication to the intended recipient(s).
19	0b	RW	GPIO Input Route SCI (GPIROUTSCI) Determines if the pad can be routed to cause SCI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0 = Routing does not cause SCI. 1 = Routing can cause SCI Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the GPE indication to the intended recipient(s).
18	0b	RO	GPIO Input Route SMI (GPIROUTSMI) Determines if the pad can be routed to cause SMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0 = Routing does not cause SMI. 1 = Routing can cause SMI. Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the SMI indication to the intended recipient(s). This bit only applies to a GPIO that has SMI capability. Otherwise, the bit is RO.
17	0b	RO	GPIO Input Route NMI (GPIROUTNMI) Determines if the pad can be routed to cause NMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0 = Routing does not cause NMI. 1 = Routing can cause NMI. Note: This bit also affects GPI_NMI_STS. If '0', GPI_NMI_STS is always clear. If '1', GPI_NMI_STS could be set (depending on GPIOOwn setting) when there is an event. Whether a NMI indication is generated and sent to the intended recipient(s) is also depending on the corresponding GPI_NMI_EN bit. This bit only applies to a GPIO that has NMI capability. Otherwise, the bit is RO.
16:12	-	-	Reserved
11:10	See Description	RW	Pad Mode (PMODE) This field determines whether the Pad is controlled by GPIO controller logic or one of the native functions muxed onto the Pad. 0h = GPIO control the Pad. 1h = native function 1, if applicable, controls the Pad 2h = native function 2, if applicable, controls the Pad. 3h = native function 3, if applicable, controls the Pad Dedicated (unmuxed) GPIO shall report RO of all 0’s in this register field If GPIO vs. native mode is configured via soft strap, this bit has no effect. Default value is determined by the default functionality of the pad.
9	1b	RW	GPIO RX Disable (GPIORXDIS) 0 = Enable the input buffer (active low enable) of the pad. 1 = Disable the input buffer of the pad. Notes: When the input buffer is disabled, the internal pad state is always driven to '0'.
8	1b	RW	GPIO TX Disable (GPIOTXDIS) 0 = Enable the output buffer (active low enable) of the pad. 1 = Disable the output buffer of the pad; i.e. Hi-Z
7:2	-	-	Reserved
1		RO/V	GPIO RX State (GPIORXSTATE) This is the current internal RX pad state after Glitch Filter logic stage and is not affected by PMode and RXINV settings.
0	0b	RW	GPIO TX State (GPIOTXSTATE) 0 = Drive a level '0' to the TX output pad. 1 = Drive a level '1' to the TX output pad.