Port Status and Control USB2 (PORTSCXUSB3) – Offset 540 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Port Status and Control USB2 (PORTSCXUSB3) – Offset 540

The USB3 Port Status and Control registers are available at the following offsets forapplicable USB3 ports:

USB3 Port 1: 540h

USB3 port 2: 550h

USB3 port 3: 560h

USB3 port 4: 570h

USB3 port 5: 580h

USB3 port 6: 590h

Bit Range	Default	Access	Field Name and Description
31	0b	RW/1S	Warm Port Reset (WPR) When software sets this bit to 1b, the Warm Reset sequence is enabled
30	0b	RW/L	Device Removable (DR) This bit indicates if this port has a removable device. 0 = Device is removable. 1 = Device is non-removable.
29:28	-	-	Reserved
27	0b	RW/P	Wake on Over-current Enable (WOE) 0 = Disable. (Default) 1 = Enable. Writing this bit to a 1b enables the port to be sensitive to overcurrent conditions as system wake-up events.
26	0b	RW/P	Wake on Disconnect Enable (WDE) 0 = Disable. (Default) 1 = Enable. Writing this bit to a 1b enables the port to be sensitive to device disconnects as system wake-up events.
25	0b	RW/P	Wake on Connect Enable (WCE) 0 = Disable. (Default) 1 = Enable. Writing this bit to a 1b enables the port to be sensitive to device connects as system wake-up events.
24	0b	RO	Cold Attach Status (CAS) This bit indicates that far-end terminations were detected in the Disconnected state and the Root Hub Port State Machine was unable to advance to the Enabled state. Software shall clear this bit by writing a 1b to the WPR bit or the xHC shall clear this bit if the CSS bit transitions to 1.
23	0b	RW/1C	Port Config Error Change (CEC) Note: This register is sticky.
22	0b	RW/1C	Port Link State Change (PLC) 0 = No change 1 = Link Status Change This flag is set to ‘1’ due to the following Port Link State (PLS) transitions:
21	0b	RW/1C	Port Reset Change (PRC) This flag is set to ‘1’ due a '1' to '0' transition of Port Reset (PR), for example, when any reset processing on this port is complete. 0 = No change 1 = Reset Complete
20	0b	RW/1C	Over-current Change (OCC) The functionality of this bit is not dependent upon the port owner. Software clears this bit by writing a 1 to it. 0 = No change. (Default) 1 = There is a change to Overcurrent Active.
19	0b	RW/1C	Warm Port Reset Change (WRC) This bit is set when Warm Reset processing on this port completes. 0 = No change. (Default) 1 = Warm reset complete
18	0b	RW/1C	Port Enabled Disabled Change (PEC) 0 = No change. (Default) 1 = There is a change to PED bit.
17	0b	RW/1C	Connect Status Change (CSC) R/WC. This flag indicates a change has occurred in the port’s Current Connect Status (CCS) or Cold Attach Status (CAS) bits. 0 = No change. (Default) 1 = There is a change to the CCS or CAS bit. The xHC sets this bit to 1b for all changes to the port device connect status, even if system software has not cleared an existing Connect Status Change. For example, the insertion status changes twice before system software has cleared the changed condition, root hub hardware will be “setting” an already-set bit (that is, the bit will remain 1b).
16	0b	RW	Port Link State Write Strobe (LWS) 0 = When 0b, write data in PLS field is ignored. (Default) 1 = When this bit is set to 1b on a write reference to this register, this flag enables writes to the PLS field. Reads to this bit return ‘0’.
15:14	0h	RW/P	Port Indicator Control (PIC) Note: This register is sticky.
13:10	0h	RO	Port Speed (PortSpeed) A device attached to this portoperates at a speed defined by the following codes: Value Speed 0100b SuperSpeed (5Gb/s) 0101b SuperSpeedPlus (10Gb/s) All other values reserved.
9	1b	RW/P	Port Power (PP) Default value of 1.<br>0 = This port is in the powered-off state <br>1 = This port is in the powered-on state. This indicates that the port does have power.<br>
8:5	5h	RW/P	Port Link State (PLS) This field is used to power manage the port and reflects its current link state.When the port is in the Enabled state, system software may setthe link U-state by writing this field. System software may also write this field to force a Disabled to Disconnected state transition of the port. Write Value and Description: 0: The link shall transition to a U0 state from any of the U-states. 2: USB 2.0 ports only. The link should transition to the U2 State. 3: The link shall transition to a U3 state from any of the U-states.This action selectively suspends the device connected to this port.While the Port Link State = U3, the hub does not propagatedownstream-directed traffic to this port, but the hub will respondto resume signaling from the port. 5: USB 3.0 ports only. If the port is in the Disabled state (PLS =Disabled, PP = 1), then the link shall transition to a RxDetect stateand the port shall transition to the Disconnected state, elseignored. 15: USB 2.0 ports only. If the port is in the U3 state (PLS = U3),then the link shall remain in the U3 state and the port shalltransition to the U3Exit substate, else ignored.All other values IgnoredNote: The Port Link State Write Strobe (LWS) shall be set to 1b towrite this field. Read Value and Definition: 0: Link is in the U0 State 1: Link is in the U1 State 2: Link is in the U2 State 3: Link is in the U3 State (Device Suspended) 4: Link is in the Disabled State 5: Link is in the RxDetect State 6: Link is in the Inactive State 7: Link is in the Polling State 8: Link is in the Recovery State 9: Link is in the Hot Reset State 10: Link is in the Compliance Mode State 11: Link is in the Test Mode State 12–14: Reserved 15: Link is in the Resume State
4	0b	RW/1S	Port Reset (PR) When software writes a1 to this bit (from a 0), the bus reset sequence as defined in the USB Specification, Revision 2.0 is started. Software writes a 0 tothis bit to terminate the bus reset sequence. Software must keep this bit at a 1 long enough to ensure the reset sequence completes as specified in the USB Specification, Revision 2.0. USB 3.0 portsshall execute the Hot Reset sequence as defined in the USB 3.0 Specification. PR remains set until reset signaling is completed by the root hub. 1 = Port is in Reset. 0 = Port is not in Reset.
3	0b	RW	Over-current Active (OCA) 0 = This port does not have an overcurrent condition. (Default) 1 = This port currently has an overcurrent condition. This bit will automatically transition from 1 to 0 when the overcurrent condition is removed. The PCH automatically disables the port when the overcurrent active bit is 1.
2	-	-	Reserved
1	0b	RW/1C	Port Enabled Disabled (PED) Note: This register is sticky.
0	0b	RW	Current Connect Status (CCS) This value reflects the currentstate of the port, and may not correspond directly to the eventthat caused the Connect Status Change bit (Bit 1) to be set. 0 = No device is present. (Default) 1 = Device is present on port.