General Purpose Event 0 Enable [127:96] (GPE0_EN[127:96]) – Offset 7c - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

General Purpose Event 0 Enable [127:96] (GPE0_EN[127:96]) – Offset 7c

Note: This register is symmetrical to the General Purpose Event 0 Status [127:96] Register.

Note that GPE0_STS bits 95:0 are claimed by the GPIO register block.

Bit Range	Default	Access	Field Name and Description
30:19	-	-	Reserved
18	0b	RW	Wake Alarm Device Timer Enable (WADT_EN) Used to enable the setting of the WADT_STS bit to generate Wake/SMI#/SCI. This bit is reset by DSW_PWROK de-assertion.
17	-	-	Reserved
16	0b	RW	GPIO[27] Enable (LANWAKE_EN) Used to enable the setting of the LANWAKE_STS bit to generate wake/SMI#/SCI. Host wake events from the PHY through LANWAKE cannot be disabled by clearing this bit. This bit is in the RTC well.
15	0b	RW/V	GPIO Tier2 SCI EN (GPIO_TIER2_SCI_EN) Used to enable the setting of GPIO_TIER2_SCI_STS to generate wake/SCI#.
14	0b	RW/V	eSPI SCI Enable (ESPI_SCI_EN) Used to enable the setting of the ESPI_SCI_STS bit to generate a SCI.
13	0b	RW/V	PME_B0 Enable (PME_B0_EN) Enables the setting of the PME_B0_STS bit to generate a wake event and/or an SCI or SMI#. This bit is reset by RTCRST# assertion.
12	0b	RW/V	ME SCI Enable (ME_SCI_EN) Used to enable the setting of the ME_SCI_STS bit to generate a SCI.
11	0b	RW/V	Power Management Event Enable (PME_EN) Enables the setting of the PME_STS to generate a wake event and/or an SCI. This bit is reset by RTCRST# assertion.
10	0b	RW/V	Low Battery Enable (BATLOW_EN) In Mobile Mode, this bit enables the BATLOW# signal to cause an SMI# or SCI (depending on the SCI_EN bit) when it goes low.This bit does not prevent the BATLOW# signal from inhibiting the wake event. In Desktop Mode this bit will be treated as Reserved. This bit is reset by RTCRST# assertion.
9	0b	RW/V	PCI Express Enable (PCI_EXP_EN) Enables PCH to cause an SCI when PCI_EXP_STS bit is set. This is used to allow the PCI Express ports, including the link to the MCH, to cause an SCI due to wake/PME events.
8:7	-	-	Reserved
6	0b	RW/V	TCOSCI Enable (TCOSCI_EN) When TCOSCI_EN and TCOSCI_STS are both set, an SCI will be generated. This bit is reset by RSMRST# assetion.
5:3	-	-	Reserved
2	0b	RW/V	Software GPE Enable (SWGPE_EN) This bit, when set to 1, enables the SW GPE function. If SWGPE_CTRL is written to a 1, hardware will set SWGPE_STS (acts as a level input) If SWGPE_STS, SWGPE_EN, and SCI_EN are all 1's, an SCI will be generated If SWGPE_STS = 1, SWGPE_EN = 1, SCI_EN = 0, and GBL_SMI_EN = 1 then an SMI# will be generated
1	0b	RW/V	Hot Plug Enable (HOT_PLUG_EN) Enables PCH to cause an SCI when the HOT_PLUG_STS bit is set. This is used to allow the PCI Express ports to cause an SCI due to hot-plug events. The following events cause HOT_PLUG_STS bit to set - Assert GPE message received from any of the PCIE ports in PCH - Assert HPGPE message received from any of the PCIE ports in PCH - Assert GPE message received downstream from CPU - Assert HPGPE message received downstream from CPU
0	-	-	Reserved