TCO1_CNT Register (TCTL1) – Offset 8 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Introduction
8254 Timer
Advanced Programmable Interrupt Controller (APIC)
APIC Indirect
CNVi PCI Configuration
DCI PCR
- DCI Control (ECTRL)
EMMC Additional
EMMC Memory Mapped
EMMC PCI Configuration
eMMC PCR
- Dynamic Clock Gating Control (GPPRVRW1)
Enhanced SPI (eSPI) PCI Configuration
eSPI PCR
FIA Configuration PCR
GbE Configuration
GbE Memory Mapped I/O
Generic SPI (GSPI) Additional
Generic SPI (GSPI) DMA Controller
Generic SPI (GSPI) Memory Mapped
GPIO Community 0
GPIO Community 1
GPIO Community 2
GPIO Community 3
GPIO Community 4
GSPI PCI Configuration
High Definition Audio (D31:F3) Memory Mapped I/O
High Definition Audio (D31:F3) PCI Configuration
HPET Memory Mapped
I2C Additional
I2C DMA Controller
I2C Memory Mapped
I2C PCI Congifuration
IDE Redirect PCI Configuration (D22:F2)
Integrated Clock (ICC) Configuration
- CMU_ONE_DWORD25 (cmu_one_dword25)
Intel RST for PCIe Storage (Remapping) PCI Configuration (D24:F0)
Intel RST for PCIe Storage MMIO
Intel(R) Management Engine Interface PCI Configuration
Intel(R) MEI MMIO
- DEVIDLE Control (HECI1_DEVIDLEC)
Intel(R) Trace Hub Configuration
Intel® HD Audio PCR
- Function Configuration (FNCFG)
Interrupt
Interrupt PCR
IO Trap
ISH
ISH PCH Configuration
ISH PCR
- Power Management Control (PMCTL)
Keyboard and Text (KT) Additional Configuration
- Power Management Control and Status (KT_CSXE_PMD_PMCSRBSE_PMCSR)
Keyboard and Text (KT) PCI Configuration (D22:F3)
LPC Configuration
LPC PCR
- General Control And Function Disable (GCFD)
OPI PCR
P2SB PCI Configuration
PCI Express* Port Configuration
PMC I/O Based
PMC Memory Mapped
PMC SSRAM PCI Configuration
Power Management Configuration
Processor Interface Memory
PSF1
PSF2
PSF3
PSF4
PSF5
RTC Indexed
RTC PCR
SATA ABAR
SATA AIDP
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Configuration
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
SATA MXTBA
SDXC (SD Card) PCR
- Dynamic Clock Gating Control (GPPRVRW1)
SDXC Additional Memory Mapped
SDXC Memory Mapped
SDXC PCI Configuration
SMBus Configuration
SMBus I/O and Memory Mapped I/O
SMBus PCR
SMBus TCO I/O
SPI Configuration
SPI Memory Mapped
Thermal Reporting Configuration
Thermal Reporting Memory Mapped
UART Additional Memory Mapped
UART DMA Controller
UART Memory Mapped
UART PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration
xHCI Configuration
xHCI Memory Mapped

TCO1_CNT Register (TCTL1) – Offset 8

TCO1_CNT Register

Bit Range	Default	Access	Field Name and Description
14:13	-	-	Reserved
12	0b	RW	(TCO_LOCK) When set to 1, this bit prevents writes from changing the TCO_EN bit (in offset 30h of Power Management I/O space). Once this bit is set to 1, it can not be cleared by software writing a 0 to this bit location. A core-well reset is required to change this bit from 1 to 0. This bit defaults to 0.
11	0b	RW	(TCO_TMR_HALT) 1 = The TCO timer will halt. It will not count, and thus cannot reach a value that would cause an SMI# or to cause the SECOND_TO_STS bit to be set. This will also prevent rebooting. 0 = The TCO timer is enabled to count. This is the default.
10	-	-	Reserved
9	0b	RW	(NMI2SMI_EN) This bit is implemented as RW but has no effect on HW. The NMI2SMI_EN bit is moved to the NMI Control register under Interrupt PCR space. Refer to NMI control register for details.
8	0b	RW	(NMI_NOW) This bit is implemented as RW but has no effect on HW. The NMI2SMI_EN bit is moved to the NMI Control register under Interrupt PCR space. Refer to NMI control register for details.
7:1	-	-	Reserved
0	0b	RW	NO_REBOOT_MSUS (NR_MSUS) This bit reflects the No Reboot pin strap state. It is sampled high on PWROK. This bit may be set or cleared by software if the strap is sampled low but may not override the strap when the it indicates No Reboot. When set, the TCO timer will count down and generate the SMI# on the first timeout, but will not reboot on the second timeout.

TCO2_CNT Register (TCTL2)

TCO2_STS Register (TSTS2) TCO2_CNT Register (TCTL2)