Slot Control; Slot Status (SLCTL_SLSTS) – Offset 58 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Slot Control; Slot Status (SLCTL_SLSTS) – Offset 58

Bit Range	Default	Access	Field Name and Description
30:25	-	-	Reserved
24	0b	RW/1C/V	Data Link Layer State Changed (DLLSC) This bit is set when the value reported in Data Link Layer Link Active field of the Link Status register is changed. In response to a Data Link Layer State Changed event, software must read Data Link Layer Link Active field of the Link Status register to determine if the link is active before initiating configuration cycles to the hot plugged device.
23	0b	RO	Electromechanical Interlock Status (EMIS) Reserved as this port does not support and electromechanical interlock.
22	0b	RO/V	Presence Detect State (PDS) If XCAP.SI is set (indicating that this root port spawns a slot), then this bit indicates whether a device is connected ('1) or empty ('0). If XCAP.SI is cleared, this bit is a '1.
21	0b	RO	MRL Sensor State (MS) Reserved as the MRL sensor is not implemented.
20	0b	RO	Command Completed (CC) This register is RO as this port does not implement a Hot Plug Controller..
19	0b	RW/1C/V	Presence Detect Changed (PDC) This bit is set by the root port when the SLSTS.PDS bit changes state.
18	0b	RO	MRL Sensor Changed (MSC) Reserved as the MRL sensor is not implemented.
17	0b	RO	Power Fault Detected (PFD) Reserved as a power controller is not implemented.
16	0b	RO	Attention Button Pressed (ABP) This register is RO as this port does not implement an attention button
15:13	-	-	Reserved
12	0b	RW	Data Link Layer State Changed Enable (DLLSCE) When set, this field enables generation of a hot plug interrupt when the Data Link Layer Link Active field is changed
11	0b	RO	Electromechanical Interlock Control (EMIC) Reserved as this port does not support an Electromechanical Interlock.
10	0b	RO	Power Controller Control (PCC) This bit has no meaning for module based hot plug.
9:8	00b	RO	Power Indicator Control (PIC) This register is RO as this port does not implement a Hot Plug Controller..
7:6	00b	RO	Attention Indicator Control (AIC) This register is RO as this port does not implement a Hot Plug Controller..
5	0b	RW	Hot Plug Interrupt Enable (HPE) When set, enables generation of a hot plug interrupt on enabled hot plug events.
4	0b	RO	Command Completed Interrupt Enable (CCE) This register is RO as this port does not implement a Hot Plug Controller..
3	0b	RW	Presence Detect Changed Enable (PDE) When set, enables the generation of a hot plug interrupt or wake message when the presence detect logic changes state.
2	0b	RO	MRL Sensor Changed Enable (MSE) This register is RO as this port does not implement a Hot Plug Controller..
1	0b	RO	Power Fault Detected Enable (PFE) This register is RO as this port does not implement a Hot Plug Controller...
0	0b	RO	Attention Button Pressed Enable (ABE) This register is RO as this port does not implement a Hot Plug Controller..