Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Miscellaneous Port Configuration 2 (MPC2) – Offset d4
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:5 | - | - | Reserved
|
4 | 0b | RW | ASPM Control Override Enable (ASPMCOEN) When set to '1', the PCIe Root Port will use the values in the ASPM Control Override registers instead of ASPM Registers in the Link Control register. This register allows BIOS to control the DMI ASPM settings instead of the OS. |
3:2 | 00b | RW | ASPM Control Override (ASPMCO) Provides BIOS control of whether root port should enter L0s or L1 or both. |
1 | 0b | RW | EOI Forwarding Disable (EOIFD) 0 = Broadcast EOI messages that are sent on the backbone are claimed by this port and forwarded across the PCIe* link.{br]1 = Broadcast EOI messages are not claimed on the backbone by this port and will not be forwarded across the PCIe* Link. |
0 | 0b | RW | L1 Completion Timeout Mode (L1CTM) 0 = PCI Express* Specification Compliant. Completion timeout is disabled during software initiated L1, and enabled during ASPM initiate L1. |