Trap Status Register (TRPSTS) – Offset 1e00 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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Trap Status Register (TRPSTS) – Offset 1e00

Bit Range	Default	Access	Field Name and Description
30:4	-	-	Reserved
3:0	0h	RW/1C/V	Cycle Trap SMI# Status (SMISTAT) These bits are set by hardware when the corresponding Cycle Trap register is enabled and a matching cycle is received (and trapped). These bits are OR'ed together to create a single status bit in the Power Management register space.Note that the SMI# and trapping must be enabled in order to set these bits. This is because, in order to do the cycle comparison, packets must be delayed by several clocks from the DMI pins to the internal receiver. This delay is only enabled when at least one of the trap ranges is enabled. These bits are set before the completion is generated for the trapped cycle, thereby guaranteeing that the processor can enter the SMI# handler when the instruction completes. Each status bit is cleared by writing a '1' to the corresponding bit location in this register.

Bit Range

Default

Access

Field Name and Description

30:4

Reserved

3:0

RW/1C/V

Cycle Trap SMI# Status (SMISTAT)

These bits are set by hardware when the corresponding Cycle Trap register is enabled and a matching cycle is received (and trapped). These bits are OR'ed together to create a single status bit in the Power Management register space.Note that the SMI# and trapping must be enabled in order to set these bits. This is because, in order to do the cycle comparison, packets must be delayed by several clocks from the DMI pins to the internal receiver. This delay is only enabled when at least one of the trap ranges is enabled. These bits are set before the completion is generated for the trapped cycle, thereby guaranteeing that the processor can enter the SMI# handler when the instruction completes. Each status bit is cleared by writing a '1' to the corresponding bit location in this register.

Trapped Cycle Register (TRPCYC1)

PSTH Control Register (PSTHCTL) Trapped Cycle Register (TRPCYC1)