Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
DMA Transfer Configuration Low (CFG_LO0) – Offset 840
NOTE: CFG_LO0 is for DMA Channel 0. The same register definition, CFG_LO1, is available for Channel 1 at address 898h.
CFG_LO0(CH0): offset 840h
CFG_LO1(CH1): offset 898h
This register contains fields that configure the DMA transfer. The channel configuration register remains fixed for all blocks of a multi-block transfer. This Register should be programmed to enabling the channel
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0h | RW | Automatic Destination Reload (RELOAD_DST) Automatic Destination Reload. The DARn register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. |
30 | 0h | RW | Automatic Source Reload (RELOAD_SRC) Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. |
29:22 | - | - | Reserved
|
21 | 0h | RW | Source Burst Length (SRC_OPT_BL) Optimize Source Burst Length: |
20 | 0h | RW | Destination Burst Length (DST_OPT_BL) Optimize Destination Burst Length : |
19 | 0h | RW | Source Handshaking Interface Polarity (SRC_HS_POL) Source Handshaking Interface Polarity. |
18 | 0h | RW | Destination Handshaking Interface Polarity (DST_HS_POL) Destination Handshaking Interface Polarity. |
17:11 | - | - | Reserved
|
10 | 0b | RW | Channel FIFO Drain (CH_DRAIN) Forces channel FIFO to drain while in suspension. This bit has effect only when CH_SUSPEND ia asserted |
9 | 1b | RO | FIFO Empty (FIFO_EMPTY) Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel. |
8 | 0h | RW | Channel Suspend (CH_SUSP) Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFGx.FIFO_EMPTY to cleanly disable a channel without losing any data. |
7 | 0h | RW | Source Status Update Enable (SS_UPD_EN) Source Status Update Enable. Source status information is fetched only from the location pointed to by the SSTATARn register, stored in the SSTATn register and written out to the SSTATn location of the LLI if SS_UPD_EN is high. This bit is ignored if (LLP_EN == 0) or (LLP_WB_EN == 0) |
6 | 0h | RW | Destination Status Update Enable (DS_UPD_EN) Destination Status Update Enable. Destination status information is fetched only from the location pointed to by the DSTATARn register, stored in the DSTATn register and written out to the DSTATn location of the LLI if DS_UPD_EN is high. This bit is ignored if (LLP_EN == 0) or (LLP_WB_EN == 0) |
5 | 0h | RW | CTL_HI Update Enable (CTL_HI_UPD_EN) CTL_HI Update Enable. If set, the CTL_HI register is written out to the CTL_HIn location of the LLI. This bit is ignored if (LLP_EN == 0) or (LLP_WB_EN == 0) |
4 | - | - | Reserved
|
3 | 0h | RW | Handshake Non-Posted Write (HSHAKE_NP_WR) 0x1 : Issues Non-Posted writes on HW-Handshake on DMA Write Port |
2 | 0h | RW | Non Posted Write (ALL_NP_WR) 0x1 : Forces ALL writes to be Non-Posted on DMA Write Port |
1 | 1h | RW | Source Burst Align (SRC_BURST_ALIGN) 0x1 : SRC Burst Transfers are broken at a Burst Length aligned boundary |
0 | 1h | RW | Destination Burst Align (DST_BURST_ALIGN) 0x1 : DST Burst Transfers are broken at a Burst Length aligned boundary |