Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Input/Output Stream Descriptor x Status (ISD0STS) – Offset 83
NOTE: This register applies to the following input and output streams at the corresponding offsets:
Input stream 0: offset 83h
Input stream 1: offset A3h
Input stream 2: offset C3h
Input stream 3: offset E3h
Input stream 4: offset 103h
Input stream 5: offset 123h
Input stream 6: offset 143h
Input stream 7: offset 283h
Input stream 8: offset 2A3h
Input stream 9: offset 2C3h
Input stream 10: offset 2E3h
Input stream 11: offset 303h
Input stream 12: offset 323h
Input stream 13: offset 343h
Input stream 14: offset 363h
Output stream 0: offset 163h
Output stream 1: offset 183h
Output stream 2: offset 1A3h
Output stream 3: offset 1C3h
Output stream 4: offset 1E3h
Output stream 5: offset 203h
Output stream 6: offset 223h
output stream 7: offset 243h
Output stream 8: offset 263h
Output stream 9: offset 383h
Output stream 10: offset 3A3h
Output stream 11: offset 3C3h
Output stream 12: offset 3E3h
Output stream 13: offset 403h
Output stream 14: offset 423h
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
6 | - | - | Reserved
|
5 | 0b | RO/V | FIFO Ready (FIFORDY) This bit defaults to 0 on reset because the FIFO is cleared on a reset. |
4 | 0b | RW/1C/V | Descriptor Error (DESE) Indicates that a serious error occurred during the fetch of a descriptor. This |
3 | 0b | RW/1C/V | FIFO Error (FIFOE) Set when a FIFO error occurs. Bit is cleared by writing a 1 to this bit position. |
2 | 0b | RW/1C/V | Buffer Completion Interrupt Status (BCIS) This bit is set to 1 by the hardware after the last sample of a buffer has been |
1:0 | - | - | Reserved
|