RTC Update In Progress SMI Control (UIPSMI) – Offset 3f04 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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RTC Update In Progress SMI Control (UIPSMI) – Offset 3f04

This register exists in the RTC well.

Bit Range	Default	Access	Field Name and Description
30:18	-	-	Reserved
17	0b	RW/1C	RTC UIP Low-to-High (UIP_L2H) This sticky status bit is set whenever the RTC Update-In-Progress signal transitions from low to high (i.e., at the start of an update).
16	0b	RW/1C	RTC UIP High-to-Low (UIP_H2L) This sticky status bit is set whenever the RTC Update-In-Progress signal transitions from high to low (i.e., at the start of an update).
15:2	-	-	Reserved
1	0b	RW	RTC UIP Low-to-High SMI Enable (UIP_L2H_SMI_en) When this bit is set, a '1' in bit 17 will assert the internal SMI signal to the Power Management SMI logic.
0	0b	RW	RTC UIP High-to-Low SMI Enable (UIP_H2L_SMI_en) When this bit is set, a '1' in bit 16 will assert the internal SMI signal to the Power Management SMI logic.

SATA ABAR

Backed Up Control (BUC) SATA ABAR