Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
NMI Status (GPI_NMI_STS_GPP_E_0) – Offset 1c4
Register bits in this register are implemented for GPP_E signals that have NMI capability only. Other bits are reserved and RO.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:17 | - | - | Reserved
|
16 | 0b | RW/1C | GPI NMI Status (GPI_NMI_STS_GPPC_E_16) Same description as bit 0. |
15 | 0b | RW/1C | GPI NMI Status (GPI_NMI_STS_GPPC_E_15) Same description as bit 0. |
14 | 0b | RW/1C | GPI NMI Status (GPI_NMI_STS_GPPC_E_14) Same description as bit 0. |
13 | 0b | RW/1C | GPI NMI Status (GPI_NMI_STS_GPPC_E_13) Same description as bit 0. |
12:9 | - | - | Reserved
|
8 | 0b | RW/1C | GPI NMI Status (GPI_NMI_STS_GPPC_E_8) Same description as bit 0. |
7 | 0b | RW/1C | GPI NMI Status (GPI_NMI_STS_GPPC_E_7) Same description as bit 0. |
6 | 0b | RW/1C | GPI NMI Status (GPI_NMI_STS_GPPC_E_6) Same description as bit 0. |
5 | 0b | RW/1C | GPI NMI Status (GPI_NMI_STS_GPPC_E_5) Same description as bit 0. |
4 | 0b | RW/1C | GPI NMI Status (GPI_NMI_STS_GPPC_E_4) Same description as bit 0. |
3 | 0b | RW/1C | GPI NMI Status (GPI_NMI_STS_GPPC_E_3) Same description as bit 0. |
2 | 0b | RW/1C | GPI NMI Status (GPI_NMI_STS_GPPC_E_2) Same description as bit 0. |
1 | 0b | RW/1C | GPI NMI Status (GPI_NMI_STS_GPPC_E_1) Same description as bit 0. |
0 | 0b | RW/1C | GPI NMI Status (GPI_NMI_STS_GPPC_E_0) This bit is set to 1 by hardware when an edge event is detected (SeeRxEdCfg, RxInv) on pad and all the following conditions are true: |