Command (CMD) – Offset 4 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Command (CMD) – Offset 4

Bit Range	Default	Access	Field Name and Description
30	0h	RW/1C	Signaled System Error (SSE) This bit is set when the device has detected an un-correctable error and reported it via SERR message over sideband. This requires SERR Enable bit to be set in Command register.
29	0h	RW/1C	Received Master Abort Status (RMA) This bit is set when device receives a Completion transaction with Unsupported Request completion status. No error will be reported.
28	0h	RW/1C	Received Target Abort Status (RTA) This bit is set when device receives a Completion transaction with Completer Abort completion status. No error will be reported
27	0h	RW/1C	Signaled Target Abort Status (STA) Set by the device when aborting a request that violates the device programming model. When SERR Enable is set SERR message will be send over sideband.
26:21	-	-	Reserved
20	1h	RO	Capabilities List (CLIST) Indicates the controller contains a capabilities pointer list and the capability pointer register is implemented at offset 0x40 in the configuration space
19	0h	RO	Interrupt Status (INSTAT) Reflects the state of the interrupt pin at the input of the enable/disable circuit. When the interrupt is asserted, and cleared when the interrupt is cleared (independent of the state of Interrupt Disable bit in command register. This bit is only associated with the INTx messages and has no meaning if the device is using MSI.
18:11	-	-	Reserved
10	0h	RW	Interrupt Disable (IntDis) Disables the function to generate INTx interrupt. A value of 0 enables the function to generate INTA messages on IOSF sideband. Note: this bit has no effect on MSI generation.
9	-	-	Reserved
8	0h	RW	System Error Enable (SERREn) Setting this bit enables the generation of System Error message, when required through sideband interface.
7:3	-	-	Reserved
2	0h	RW	Bus Master Enable (BME) When set enables the ability to issue Memory or IO requests, including MSI.
1	0h	RW	Memory Space Enable (MEM) When set, Memory Space Decoding is enabled and memory transactions targeting the device are accepted. Note: The MSE has to be set to accept any memory transaction on the primary interface targeting any of Trace Hub's BARs.
0	-	-	Reserved