Control Register Low (CTL_LO0) – Offset 818 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Control Register Low (CTL_LO0) – Offset 818

NOTE: CTL_LO0 is for DMA Channel 0. The same register definition, CTL_LO1, is available for Channel 1 at address 870h.

LLP_HI0 (CH0): offset 818h

LLP_LO1 (CH1): offset 870h

This register contains fields that control the DMA transfer. The CTL_HI register is part of the block descriptor (linked list item - LLI) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is enabled. If status write-back is enabled, CTL_HI is written to then control registers location of the LLI in system memory at the end of the block transfer.

Bit Range	Default	Access	Field Name and Description
30:29	-	-	Reserved
28	0h	RW	(LLP_SRC_EN) Block chaining is enabled on the source side only if the LLP_SRC_EN field is high and LLPn.LOC is non-zero and (LLP_EN == 1)
27	0h	RW	(LLP_DST_EN) Block chaining is enabled on the destination side only if the LLP_DST_EN field is high and LLPn.LOC is non-zero and (LLP_EN == 1)
26:22	-	-	Reserved
21:20	0h	RW	(TT_FC) The following transfer types are supported. Memory to Memory (00) Memory to Peripheral (01) Peripheral to Memory (10) Peripheral to Peripheral (11) Flow Control is always assigned to the DMA.
19	-	-	Reserved
18	0h	RW	(DST_SCATTER_EN) 0 = Scatter disabled 1 = Scatter enabled Scatter on the destination side is applicable only when the CTL_LOn.DINC bit indicates an incrementing address control.
17	0h	RW	(SRC_GATHER_EN) 0 = Gather disabled 1 = Gather enabled Gather on the source side is applicable only when the CTL_LOn.SINC bit indicates an incrementing address control.
16:14	0h	RW	(SRC_MSIZE) Number of data items, each of width CTL_LOn.SRC_TR_WIDTH, to be read from the source.
13:11	0h	RW	(DEST_MSIZE) Number of data items, each of width CTL_LOn.DST_TR_WIDTH, to be written to the destination.
10	0h	RW	(SINC) Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change. 0 = Increment 1 = Fixed (No Change)
9	-	-	Reserved
8	0h	RW	(DINC) Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No change. 0 = Increment 1 = Fixed (No change)
7	-	-	Reserved
6:4	0h	RW	(SRC_TR_WIDTH) BURST_SIZE = (2 ^ MSIZE) 1. Transferred Bytes Per Burst = (BURST_SIZE * TR_WIDTH) 2. For incrementing addresses and (Transfer_Width < 4 Bytes), the MSIZE parameter is ignored since only single transactions are supported (due to OCP limitations)
3:1	0h	RW	(DST_TR_WIDTH) Destination Transfer Width. BURST_SIZE = (2 ^ MSIZE) 1.Transferred Bytes Per Burst = (BURST_SIZE * TR_WIDTH) 2.For incrementing addresses and (Transfer_Width < 4 Bytes), the MSIZE parameter is ignored since only single transactions are supported (due to OCP limitations)
0	0h	RW	(INT_EN) Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled.