Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Error Interrupt Status Enable (errorintrstsena) – Offset 36
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
14:12 | - | - | Reserved
|
11 | 0h | RW | Reponse Error Status Enable (response_err_sts_enb) 0 - Masked |
10 | 0h | RW | Tuning error status enable (tuning_err_sts_enb) 0 - Masked |
9 | 0h | RW | ADMA Error Status Enable (adma_err_sts_enb) 0 - Masked |
8 | 0h | RW | Auto CMD12 Error Status Enable (auto_cmd_err_sts_enb) 0 - Masked |
7 | 0h | RW | Current Limit Error Status Enable (current_limit_err_sts_enb) 0 - Masked |
6 | 0h | RW | Data End Bit Error Status Enable (data_end_bit_err_sts_enb) 0 - Masked |
5 | 0h | RW | Data CRC Error Status Enable (data_crc_err_sd_mode) 0 - Masked |
4 | 0h | RW | Data Timeout Error Status Enable (data_timeout_err_sd_mode) 0 - Masked |
3 | 0h | RW | Command Index Error Status Enable (cmd_index_err_sd_mode) 0 - Masked |
2 | 0h | RW | Command End Bit Error Status Enable (cmd_end_bit_err_sd_mode) 0 - Masked |
1 | 0h | RW | Command CRC Error Status Enable (cmd_crc_err_sd_mode) 0 - Masked |
0 | 0h | RW | Command Timeout Error Status Enable (cmd_timeout_err_sd_mode) 0 - Masked |