Device Status Register (DSTS) – Offset c70c - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Device Status Register (DSTS) – Offset c70c

Bit Range	Default	Access	Field Name and Description
30	-	-	Reserved
29	0h	RO	Device Controller Not Ready (DCNRD) The bit indicates that the core is in the process of completing the state transitions after exiting from hibernation. To complete the state transitions, it takes 256 bus clock cycles from the time DCTL[31].Run/Stop is set. During hibernation, if the UTMI/ULPI PHY is in suspended state, then the 256-bus clock cycle delay starts after the PHY exited suspended state. Software must set DCTL[31].Run/Stop to '1' and wait for this bit to be de-asserted to zero before processing DSTS.USBLnkSt. This bit is valid only when DWC_USB3_EN_PWROPT is set to two and GCTL[1].GblHibernationEn =1.
28:26	-	-	Reserved
25	0h	RO	Restore State Status (RSS) When the controller has finished the restore process, it will complete the command by setting DSTS.RSS to '0'.
24	0h	RO	Save State Status (SSS) When the controller has finished the save process, it will complete the command by setting DSTS.SSS to '0'.
23	0h	RO	Core Idle (COREIDLE) The bit indicates that the core finished transferring all RxFIFO data to system memory, writing out all completed descriptors, and all Event Counts are zero.
22	1h	RO	Device Controller Halted (DEVCTRLHLT) This bit is set to 0 when the Run/Stop bit in the DCTL register is set to 1. The core sets this bit to 1 when, after SW sets Run/Stop to ‘0’, the core is idle and the lower layer finishes the disconnect process. When Halted =1, the core does not generate Device events.
21:18	4h	RO	USB/Link State (USBLNKST) In SS mode: 4'h0: U0 4'h1: U1 4'h2: U2 4'h3: U3 4'h4: SS_DIS 4'h5: RX_DET 4'h6: SS_INACT 4'h7: POLL 4'h8: RECOV 4'h9: HRESET 4'ha: CMPLY 4'hb: LPBK 4'hf: Resume/Reset In HS/FS/LS mode: 4’h0: On state 4’h2: Sleep (L1) state 4’h3: Suspend (L2) state 4’h4: Disconnected state 4’h5: Early Suspend state 4'he: Reset 4'hf: Resume
17	0001h	RO	RxFIFO Empty (RXFIFOEMPTY)
16:3	0000h	RO	Frame/Microframe Number of the Received SOF (SOFFN) When the core is operating at high-speed: [16:6] indicates the frame number [5:3] indicates the microframe number When the core is operating at full-speed: [16:14] is not used. Software can ignore these 3 bits [13:3] indicates the frame number
2:0	4h	RO	Connected Speed (CONNECTSPD) Indicates the speed at which the core has come up after speed detection through a chirp sequence: 3’b100: SuperSpeed 3’b000: High-speed 3’b001: Full-speed 3’b010: Low-speed 3’b011: Full-speed