Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Input/Output Stream Descriptor x Format (ISD0FMT) – Offset 92
NOTE: This register applies to the following input and output streams at the corresponding offsets:
Input stream 0: offset 92h
Input stream 1: offset B2h
Input stream 2: offset D2h
Input stream 3: offset F2h
Input stream 4: offset 112h
Input stream 5: offset 132h
Input stream 6: offset 152h
Input stream 7: offset 292h
Input stream 8: offset 2B2h
Input stream 9: offset 2D2h
Input stream 10: offset 2F2h
Input stream 11: offset 312h
Input stream 12: offset 332h
Input stream 13: offset 352h
Input stream 14: offset 372h
Output stream 0: offset 172h
Output stream 1: offset 192h
Output stream 2: offset 1B2h
Output stream 3: offset 1D2h
Output stream 4: offset 1F2h
Output stream 5: offset 212h
Output stream 6: offset 232h
output stream 7: offset 252h
Output stream 8: offset 272h
Output stream 9: offset 392h
Output stream 10: offset 3B2h
Output stream 11: offset 3D2h
Output stream 12: offset 3F2h
Output stream 13: offset 412h
Output stream 14: offset 432h
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
14 | 0b | RW | Sample Base Rate (BASE) 0=48 kHz |
13:11 | 000b | RW | Sample Base Rate Multiple (MULT) 000=48 kHz/44.1 kHz or less |
10:8 | 000b | RW | Sample Base Rate Divisor (DIV) 000=Divide by 1 (48 kHz, 44.1 kHz) |
7 | - | - | Reserved
|
6:4 | 000b | RW | Bits per Sample (BITS) 000=8 bits. The data will be packed in memory in 8bit containers on 16bit boundaries |
3:0 | 0000b | RW | Number of Channels (CHAN) Number of channels in each frame of the stream: |