Power Management Control And Status (PCS) – Offset 54
PMES and PMEE bits reside in Resume well, and reset by resume reset.
Bit Range | Default | Access | Field Name and Description |
31:24 | 00h | RO | Data (DT) Does not apply. Hardwired to 0's. |
23 | 0b | RO | Bus Power/Clock Control Enable (BPCCE) Does not apply. Hardwired to0. |
22 | 0b | RO | B2/B3 Support (B23) Does not apply. Hardwired to 0. |
21:16 | - | - | Reserved |
15 | 0b | RW/1C/V | PME Status (PMES) This bit is set when the Intel HD Audio controller would normally assert the PME# signal independent of the state of the PME bit. This bit is cleared on a power-on reset. Software must not make assumptions about the reset state of this bit and must set it appropriately. |
14:9 | - | - | Reserved |
8 | 0b | RW | PME Enable (PMEE) When set, and if corresponding PMES is also set, the Intel HD Audio subsystem send PME to PMC.
This bit is cleared on a power-on reset. Software must not make assumptions about the reset state of this bit and must set it appropriately. |
7:4 | - | - | Reserved |
3 | 1b | RW/L | No Soft Reset (NSR) When set ( 1 ), this bit indicates that devices transitioning from D3hot to D0 because of PowerState commands do not perform an internal reset. Configuration Context is preserved. Upon transition from the D3hot to the D0 Initialized state, no additional operating system intervention is required to preserve Configuration Context beyond writing the PowerState bits.
When clear ( 0 ), devices do perform an internal reset upon transitioning from D3hot to D0 via software control of the PowerState bits. Configuration Context is lost when performing the soft reset. Upon transition from the D3hot to the D0 state, full reinitialization sequence is needed to return the device to D0 Initialized.
Regardless of this bit, devices that transition from D3hot to D0 by a system or bus segment reset will return to the device state D0 Uninitialized with only PME context preserved if PME is supported and enabled.
Locked when FNCFG.BCLD = 1. |
2 | - | - | Reserved |
1:0 | 00b | RW | Power State (PS) This field is used both to determine the current power state of the HD Audio subsystem and to set a new power state. 00: D0 state 11: D3HOT state If software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally, however, the data is discarded and no state change occurs. When in the D3HOT states, the HD Audio subsystem's configuration space is available, but the I/O and memory spaces are not. Additionally, interrupts are blocked. When software changes this value from the D3HOT state to the D0 state, an internal warm (soft) reset is generated, and software must re-initialize the function. |