General Configuration Register (GCR) – Offset 300 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

General Configuration Register (GCR) – Offset 300

Bit Range	Default	Access	Field Name and Description
31	0b	RW/L	Cycle Router Enable Lockdown (CREL) When this bit is set to '1', the GCR.CRE bit is locked down and cannot be written by any subsequent cycles. Once set to '1', this bit is only cleared by PLTRST#.
30	0b	RW/L	Remapping Configuration Lockdown (RCL) When this bit is set to '1', the following registers are locked down and cannot be written. Once set to '1', this bit is only cleared by PLTRST#. Memory BAR Remap Configuration (MBRC) I/O BAR Remap Source Configuration (IOBRSC) I/O BAR Remap Target Configuration (IOBRTC) Power Management Capability Remap Configuration (PMCRC) MSI Capability Remap Configuration Remap (MCRC) AHCI Index/Data Pair Capability Remap Configuration (AIDPCRC) MSI-X Capability Remap Configuration (MXCRC) MSI-X Table Remap Configuration (MXTRC) MSI-X Table Base Address Register (MXTBAR) MSI-X PBA Remap Configuration (MXPRC) MSI-X PBA Base Address Register (MXPBAR) NVM Remapping Device:Function (NRDF) Shadowed AHCI Ports Implemented (SAPI)
29	0b	RW/L	Configuration Access Index/Data Lockdown (CAIDL) When this bit is set to '1', the following configuration access index/data registers are locked down and cannot be written. Once set to '1', this bit is only cleared by PLTRST#. Configuration Access Index Register (CAIR) Configuration Access Data Register (CADR)
28:21	-	-	Reserved
20:1	00000000000000000001b	RW	PCIe Lane Selected (PLS) This field is bit significant, and it corresponds to PCIe Lane [20:1]. It selects the PCIe lane(s) associated with this Cycle Router when enabled. This field must be valid when GCR.CRE bit is set to '1'. Only PCIe lane(s) that are remap capable as indicated by GSR.PLRC shall be selected. This shall be the lane(s) where PCIe SSD device is discovered during the initialization process. The number of '1' in this field indicates the PCIe lane width configured for this Cycle Router. They must be contiguous and begin at the appropriate lane that supporting the lane width associated with the PCIe root-port configuration. GCR bit[1] (GCR.PLS[0]) corresponds to the first lane of the first PCIe root-port, i.e. PCIe Port 1 Lane [0], and so on.
0	0b	RW/L	Cycle Router Enable (CRE) When set to '1', Cycle Router is enabled. When this bit is '0', Cycle Router is disabled and will not respond to cycles except accesses to the extended configuration registers in 300h-3FFh. This bit enables the path between Cycle Router and the PCIe Root-port as well as between Cycle Router and the AHCI controller. This bit is locked down and cannot be written when GCR.CREL bit is set to '1'. When GSR.PCCS is a '1', HW inhibits the write to set GCR.CRE bit to '1' due to a mismatch port configuration detected. After correcting the port configuration, BIOS is required to clear the GSR.PCCS bit before the attempt to set the GCR.CRE bit again.