Thermal Sensor Enable And Lock (TSEL) – Offset 8 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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Thermal Sensor Enable And Lock (TSEL) – Offset 8

This register controls the operation of the thermal sensor.

Bit Range	Default	Access	Field Name and Description
7	0b	RW/1L	Policy Lock-Down Bit (PLDB) Policy Lock-Down Bit: When written to 1, this bit prevents any more writes to this register and to TTCB, Test1, Test2, Test3, Test4, Test5, Test6 and Test7 registers.
6:1	-	-	Reserved
0	0b	RW/L	Enable TS (ETS) 1: Enables the thermal sensor. Until this bit is set, no thermometer readings or trip events will occur. If SW reads the TEMP register before the sensor is enabled, it will read 0x0. The value of this bit is sent to the thermal sensor. NOTE: if the sensor is running and valid temperatures have been captured in TEMP and then ETS is cleared, TEMP will retain its old value. Clearing ETS does not force TEMP to 0x00. 0: Disables the sensor.

Bit Range

Default

Access

Field Name and Description

RW/1L

Policy Lock-Down Bit (PLDB)

Policy Lock-Down Bit: When written to 1, this bit prevents any more writes to this register and to TTCB, Test1, Test2, Test3, Test4, Test5, Test6 and Test7 registers.

6:1

Reserved

RW/L

Enable TS (ETS)

1: Enables the thermal sensor. Until this bit is set, no thermometer readings or trip events will occur. If SW reads the TEMP register before the sensor is enabled, it will read 0x0. The value of this bit is sent to the thermal sensor. NOTE: if the sensor is running and valid temperatures have been captured in TEMP and then ETS is cleared, TEMP will retain its old value. Clearing ETS does not force TEMP to 0x00.

0: Disables the sensor.

Thermal Sensor Reporting Enable And Lock (TSREL)

Thermal Sensor Status (TSS) Thermal Sensor Reporting Enable And Lock (TSREL)