Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_0) – Offset a90
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:30 | 01b | RO | Pad Reset Config (PADRSTCFG) This register controls which reset is used to reset GPIO pad register fields in PAD_CFG_DW0 and PAD_CFG_DW1 registers. This bit is hardwired to 01 |
29:24 | - | - | Reserved
|
23 | 0b | RW | RX Invert (RXINV) This bit determines if the selected pad state should go through the polarity inversion stage. This field only makes sense when the RX buffer is configured as an input in either GPIO Mode or native function mode.This bit does not affect GPIORXState. |
22:11 | - | - | Reserved
|
10 | 0b | RO | Pad Mode (PMODE) This field determines whether the Pad is controlled by GPIO controller logic or one of the native functions muxed onto the Pad.0h = GPIO control the Pad |
9 | 0b | RW | GPIO RX Disable (GPIORXDIS) 0 = Enable the input buffer (active low enable) of the pad |
8 | 0b | RW | GPIO TX Disable (GPIOTXDIS) 0 = Enable the output buffer (active low enable) of the pad |
7:2 | - | - | Reserved
|
1 |
| RO/V | GPIO RX State (GPIORXSTATE) This is the current internal RX pad state after Glitch Filter logic stage and hardware debouncer (if any) and is not affected by PMode and RXINV settings. |
0 | 1b | RW | GPIO TX State (GPIOTXSTATE) 0 = Drive a level '0' to the TX output pad |