D0I3 Control (IPC_d0i3C_reg) – Offset 6d0 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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D0I3 Control (IPC_d0i3C_reg) – Offset 6d0

This is a 32 bit register which is set to 0 on a system reset or a wakeup from D3Cold. When ME writes to any of these bits with 1, an interrupt is generated. The Interrupt is then cleared by writing 1`b1 to this register after the appropriate ISR is serviced.

Bit Range	Default	Access	Field Name and Description
30:4	-	-	Reserved
3	1h	RW/1C	Restore Required (ISH_IPC_d0i3C_reg3) Restore Required bit.
2	0h	RW	D0i3 (ISH_IPC_d0i3C_reg2) SW sets this bit to ‘1’ to move the controller into the D0i3 state.Writing this bit to ‘0’ will return the controller to the fully active D0 state (D0i0).Note that this bit is treated by ISH FW as an D0i3 allow indication from SW. Thismeans that if this bit is set to 1, then ISH may be in D0i3 state and if this bit is set to0, then ISH is precluded from being in D0i3 state.
1	0h	RW	Interrupt Request (ISH_IPC_d0i3C_reg1) SW sets this bit to ‘1’ to ask for an interrupt to begenerated on completion of the command. SW must clear or set this on each write to this register.
0	0h	RW/1C	Command-in-Progress (ISH_IPC_d0i3C_reg0) HW sets this bit on a 1->0 or 0->1 transition of bit2. While set, the other bits in this register are not valid and it is illegal for SW towrite to any bit in this register. When clear all the other bits in the register are valid and SW may write to any bit.ISH FW will clear this bit, upon internal logging of the D0i3 allow/disallow (1 or 0state of bit2) indication.

ISH PCH Configuration

Remap 0 (REMAP0) ISH PCH Configuration