I2C Interrupt Status (IC_INTR_STAT) – Offset 2c - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

I2C Interrupt Status (IC_INTR_STAT) – Offset 2c

Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register

Bit Range	Default	Access	Field Name and Description
30:14	-	-	Reserved
13	0h	RO	R_MST_ON_HOLD (R_MST_ON_HOLD) Indicates whether a master is holding the bus and the TX FIFO is empty.Enabled only when I2C_DYNAMIC_TAR_UPDATE = 1 andIC_EMPTYFIFO_HOLD_MASTER_EN = 1
12	-	-	Reserved
11	0h	RO	R_GEN_CALL (R_GEN_CALL) Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling the controller or when the processor reads bit 0 of the IC_CLR_GEN_CALL register
10	0h	RO	R_START_DET (R_START_DET) Indicates whether a START or RESTART condition has occurred on the I2C interface
9	0h	RO	R_STOP_DET (R_STOP_DET) Indicates whether a STOP condition has occurred on the I2C interface.
8	0h	RO	R_ACTIVITY (R_ACTIVITY) This bit captures the controller activity and stays set until it is cleared. There are four ways to clear it:1. Disabling the controller,2. Reading the IC_CLR_ACTIVITY register,3. Reading the IC_CLR_INTR register,4. System resetNote: Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller is idle, this bit remains set until cleared, indicating that there was activity on the bus.
7	-	-	Reserved
6	0h	RO	R_TX_ABRT (R_TX_ABRT) This bit indicates if the controler, as an I2C transmitter, is unable to completethe intended actions on the contents of the transmit FIFO. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates thereason why the transmit abort takes places.NOTE: The controller flushes/resets/empties the TX FIFO whenever thisbit is set. The TX FIFO remains in this flushed state until the registerIC_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is thenready to accept more data bytes.
5	-	-	Reserved
4	0h	RO	R_TX_EMPTY (R_TX_EMPTY) The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0:This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1:This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. Then the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.
3	0h	RO	R_TX_OVER (R_TX_OVER) Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register.
2	0h	RO	R_RX_FULL (R_RX_FULL) Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. NOTE: If IC_RX_FULL_HLD_BUS_EN=1, then the RX_OVER interrupt isnever set to 1, because the criteria to set this interrupt are never met.
1	0h	RO	R_RX_OVER (R_RX_OVER) Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost.
0	0h	RO	R_RX_UNDER (R_RX_UNDER) Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register.