Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
ID | Date | Version | Classification |
---|---|---|---|
615146 | 08/09/2019 | 1.2 | Public |
Command (CMD) – Offset 4
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
14:11 | - | - | Reserved
|
10 | 0b | RW | Interrupt Disable (ID) Enables the device to assert an INTx#. When set, the Intel(r) HD Audio controller's INTx# signal will be de-asserted. When cleared, the INTx# signal may be asserted. Note that this bit does not affect the generation of MSI's. |
9 | 0b | RO | Fast Back to Back Enable (FBE) Not implemented. Hardwired to 0. |
8 | 0b | RW | SERR Enable (SEN) Functionality not implemented. This bit is R/W to pass PCIe compliance testing. |
7 | 0b | RO | Wait Cycle Control (WCC) Not implemented. Hardwired to 0. |
6 | 0b | RW | Parity Error Response (PER) Functionality not implemented. This bit is R/W to pass PCIe compliance testing. |
5 | 0b | RO | VGA Palette Snoop (VPS) Not implemented. Hardwired to 0. |
4 | 0b | RO | Memory Write and Invalidate Enable (MWI) Not implemented. Hardwired to 0. |
3 | 0b | RO | Special Cycle Enable (SCE) Not implemented. Hardwired to 0. |
2 | 0b | RW | Bus Master Enable (BME) 1 = Enable, 0 = Disable. Controls standard PCI Express bus mastering capabilities for Memory and IO, reads and writes. Note that this also controls MSI generation since MSI are essentially Memory writes. |
1 | 0b | RW | Memory Space Enable (MSE) When set, enables memory space accesses to the Intel HD Audio controller. |
0 | 0b | RO | I/O Space (IOS) The Intel HD Audio controller does not implement IO Space, therefore |