Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
USB Legacy Support Capability (USBLEGSUP) – Offset 846c
This register is modified and maintained by BIOS
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:25 | - | - | Reserved
|
24 | 0b | RW | HC OS Owned Semaphore (HCOSOS) Default = ‘0’. System software sets this bit to request ownership of the xHC. Ownership is obtained when this bit reads as ‘1’ and the HC BIOS Owned Semaphore bit reads as ‘0’. |
23:17 | - | - | Reserved
|
16 | 0b | RW | HC BIOS Owned Semaphore (HCBIOSOS) Default = ‘0’. The BIOS sets this bit to establish ownership of the xHC. System BIOS will set this bit to a ‘0’ in response to a request for ownership of the xHC by system software. |
15:8 | 22h | RW/L | Next Capability Pointer (NextCP) This field indicates the location of the next capability with respect to the effective address of this capability. Refer to Table 145 for more information on this field. |
7:0 | 01h | RW/L | Capability ID (CID) This field identifies the extended capability. Refer to Table 146 for the value that identifies the capability as Legacy Support.This extended capability requires one additional 32-bit register for control/status information (USBLEGCTLSTS), and this register is located at offset xECP+04h. |