Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
SATA General Configuration (SATAGC) – Offset 9c
SATA General Configuration
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0h | RW/O | Register Lock (REGLOCK) 0 = Will not lock CAP.CP, PID.NEXT, MID.NEXT, or SATACR0.NEXT |
30:16 | - | - | Reserved
|
15 | 0h | RW | Data Phase Parity Error Enable (DPPEE) When '1', IOSF data phase parity error handling is enabled. When '0', the data phase parity error handling is disabled. |
14:12 | 0h | RW | Write Request_Size Select/Max_Payload_Size (WRRSELMPS) These two bits select the max write request size that SATA host controller will initiate for DMA write to memory. SATA host controller will internally break up larger write request based on these bits. The request is address-aligned to the selected size. |
11 | 0h | RW | Command Parity Error Enable (CPEE) When '1', command parity error handing is enable. When '0' the command parity error handling is disabled. |
10 | 0h | RW | SATA Controller Function Disable (SCFD) BIOS program this bit to 1 to disable the SATA Controller function. When 0, SATA Controller function is enabled. When disable, SATA Host Controller will not claimed the register access targeting its Configuration Space. In IOSF primary Fabric Decode scheme, it's expected BIOS also program the corresponding bit used by the Fabric Decoder accordingly hence both SATA SIP and Fabric Decoder are in sync, and BIOS need to program this bit before programming the one in Fabric Decoder. Once this bit is set, BIOS isnot able to revert it back to Function Enable until next round of platform reset. This register field is not reset by FLR. |
9 | 0h | RW | Unsupported Request Reporting Enable (URRE) If set to 1 by software, it allows reporting of an Unsupported Request as a system error. If both URRE and PCI configuration SERR# Enable registers are set to a 1, then the agent must set the Signaled System Error bit in the PCI Status register and send a DO_SERR message in IOSF-SB interface. |
8 | 0h | RW/1C/V | Unsupported Request Detected (URD) Set to 1 by hardware upon detecting an Unsupported Request on IOSF Primary interface that is not considered Advisory Non-Fatal. Cleared to 0 by SW. URD bit is only set based on IOSF primary bus interface activity. Its not set based on IOSF sideband bus interface activity. |
7 | 0h | RW/O | Alternate ID Enable (AIE) 0 = Clearing this bit when in RAID mode, the SATA Controller located at Device 23: Function 0 will report its In-box Compatibility ID. Refer to the Device and Revision ID Table in Vol1 for more info. Clearing this bit is required for the Intel® Rapid Storage Technology driver (including the Microsoft* Windows* operating system in-box version of the driver) to load on the platform. |
6 | 0h | RW/O/V | AIE0 DevID Selection (DEVIDSEL) This register allows BIOS to select Device ID when AIE=0. This bit only has effect in Desktop / Server SKU. In Mobile SKU this bit has no effect at all. Refer to config register offset 09h PI for usage. |
5 | 0h | RW/O | FLR Capability Selection (FLRCSSEL) This allows the FLR Capability to be bypassed. Refer to config offset B0h. BIOS is required to program this bit to 1 and config offset A8h SATACR0.NEXT to 00h. |
4:3 | 0h | RW/O | MXTBA Size Select (MSS) These 2 bits select the size of the Memory space for the MSI-X Table defined in BAR 0 (Configuration space offset 10h). |
2:0 | 0h | RW/O | ABAR Size Select (ASSEL) These 3 bits select the size of the Memory space for the ABAR in BAR 5 (Configuration space offset 24h). |