System Time Control High Register (LTRCAP) – Offset a8 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Introduction
8254 Timer
Advanced Programmable Interrupt Controller (APIC)
APIC Indirect
CNVi PCI Configuration
DCI PCR
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xHCI Configuration
xHCI Memory Mapped

System Time Control High Register (LTRCAP) – Offset a8

Bit Range	Default	Access	Field Name and Description
30:29	-	-	Reserved
28:26	0x0	RW	Maximum Non-Snoop Latency Scale (MNSLS) Provides a scale for the value containedwithin the Maximum Non-Snoop Latency Value field. 000b = Value times 1 ns 001b = Value times 32 ns 010b = Value times 1,024 ns 011b = Value times 32,768 ns 100b = Value times 1,048,576 ns 101b = Value times 33,554,432 ns 110b–111b = Reserved
25:16	0x0	RW	Maximum Non-Snoop Latency (MNSL) Specifies the maximum non-snoop latency that adevice is permitted to request. Software should set this to the platform’s maximum supportedlatency or less. This field is also an indicator of the platforms maximum latency, should an endpoint send up LTRLatency Values with the Requirement bit not set.
15:13	-	-	Reserved
12:10	0x0	RW	Maximum Snoop Latency Scale (MSLS) Provides a scale for the value contained withinthe Maximum Snoop Latency Value field. 000b = Value times 1 ns 001b = Value times 32 ns 010b = Value times 1,024 ns 011b = Value times 32,768 ns 100b = Value times 1,048,576 ns 101b = Value times 33,554,432 ns 110b–111b = Reserved
9:0	0x0	RW	Maximum Snoop Latency (MSL) Specifies the maximum snoop latency that a device ispermitted to request. Software should set this to the platform’s maximum supported latency or less.This field is also an indicator of the platforms maximum latency, should an endpoint send up LTRLatency Values with the Requirement bit not set.

Capabilities List and Power Managment Capabilities Register (CLIST1_PMC)

Lock LAN Disable (LOCKLANDIS) Capabilities List and Power Managment Capabilities Register (CLIST1_PMC)