Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
SMI Status (GPI_SMI_STS_GPP_B_0) – Offset 184
Register bits in this register are implemented for GPP_B signals that have SMI capability only. Other bits are reserved and RO.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:24 | - | - | Reserved
|
23 | 0b | RW/1C | GPI SMI Status (GPI_SMI_STS_GPPC_B_23) Same description as bit 14. |
22:21 | - | - | Reserved
|
20 | 0b | RW/1C | GPI SMI Status (GPI_SMI_STS_GPPC_B_20) Same description as bit 14. |
19:15 | - | - | Reserved
|
14 | 0b | RW/1C | GPI SMI Status (GPI_SMI_STS_GPPC_B_14) This bit is set to 1 by hardware when a level event (See RxEdCfg,RxInv) is detected, and all the following conditions are true: |
13:0 | - | - | Reserved
|