BIST, Header Type, Latency Timer, And Cache Line Size (KT_HOST_BIST_HTYPE_LT_CLS) – Offset c - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Introduction
8254 Timer
Advanced Programmable Interrupt Controller (APIC)
APIC Indirect
CNVi PCI Configuration
DCI PCR
- DCI Control (ECTRL)
EMMC Additional
EMMC Memory Mapped
EMMC PCI Configuration
eMMC PCR
- Dynamic Clock Gating Control (GPPRVRW1)
Enhanced SPI (eSPI) PCI Configuration
eSPI PCR
FIA Configuration PCR
GbE Configuration
GbE Memory Mapped I/O
Generic SPI (GSPI) Additional
Generic SPI (GSPI) DMA Controller
Generic SPI (GSPI) Memory Mapped
GPIO Community 0
GPIO Community 1
GPIO Community 2
GPIO Community 3
GPIO Community 4
GSPI PCI Configuration
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High Definition Audio (D31:F3) PCI Configuration
HPET Memory Mapped
I2C Additional
I2C DMA Controller
I2C Memory Mapped
I2C PCI Congifuration
IDE Redirect PCI Configuration (D22:F2)
Integrated Clock (ICC) Configuration
- CMU_ONE_DWORD25 (cmu_one_dword25)
Intel RST for PCIe Storage (Remapping) PCI Configuration (D24:F0)
Intel RST for PCIe Storage MMIO
Intel(R) Management Engine Interface PCI Configuration
Intel(R) MEI MMIO
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Intel® HD Audio PCR
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Interrupt
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IO Trap
ISH
ISH PCH Configuration
ISH PCR
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Keyboard and Text (KT) Additional Configuration
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Keyboard and Text (KT) PCI Configuration (D22:F3)
LPC Configuration
LPC PCR
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OPI PCR
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PMC Memory Mapped
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PSF1
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PSF4
PSF5
RTC Indexed
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SDXC Additional Memory Mapped
SDXC Memory Mapped
SDXC PCI Configuration
SMBus Configuration
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SPI Memory Mapped
Thermal Reporting Configuration
Thermal Reporting Memory Mapped
UART Additional Memory Mapped
UART DMA Controller
UART Memory Mapped
UART PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration
xHCI Configuration
xHCI Memory Mapped

BIST, Header Type, Latency Timer, And Cache Line Size (KT_HOST_BIST_HTYPE_LT_CLS) – Offset c

This register contains the BIST, header type, latency timer, and cache line size values.

Bit Range	Default	Access	Field Name and Description
31:24	00h	RO	Built In Self Test (BIST) Not implemented. Hardwired to 0.
23	1b	RO/V	Header Type 1 (HTYPE1) This bit identifies whether or not the device contains multiple functions. - If the bit is 0, then the device is single function. - If the bit is 1, then the device has multiple functions.
22:16	00h	RO	Header Type 0 (HTYPE0) This field identifies the layout of the second part of the predefined header (beginning at byte 10h in Configuration Space). - The encoding 00h specifies the non-bridge Configuration Space Header. - The encoding 01h specifies the PCI-to-PCI bridge Configuration Space Header. - The encoding 02h specifies the CardBus bridge Configuration Space Header. - All other encodings are reserved. Hardwired to 0 to identify the non-bridge Configuration Space Header.
15:8	00h	RO	Latency Timer (LT) Not implemented. Hardwired to 0.
7:0	00h	RO	Cache Line Size (CLS) Not implemented. Hardwired to 0.

KT IO BAR (KT_HOST_IOBAR)

Class Code And Revision ID (KT_HOST_CC_RID) KT IO BAR (KT_HOST_IOBAR)