USB Legacy Support Control Status (USBLEGCTLSTS) – Offset 8470 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

USB Legacy Support Control Status (USBLEGCTLSTS) – Offset 8470

Bit Range	Default	Access	Field Name and Description
31	0b	RW/1C	SMI on BAR (SMIBAR) Default = ‘0’. This bit is set to ‘1’ whenever the Base Address Register (BAR) is written.
30	0b	RW/1C	SMI on PCI Command (SMIPCIC) . Default = ‘0’. This bit is set to ‘1’ whenever the PCI Command Register is written.
29	0b	RW/1C	SMI on OS Ownership Change (SMIOSOC) Default = ‘0’. This bit is set to ‘1’ whenever the HC OS Owned Semaphore bit in the USBLEGSUP register transitions from ‘1’ to a ‘0’ or ‘0’ to a ‘1’.
28:21	-	-	Reserved
20	0b	RO	SMI on Host System Error (SMIHSE) Default = ‘0’. Shadow bit of Host System Error (HSE) bit in the USBSTS register.To clear this bit to a ‘0’, system software shall write a ‘1’ to the Host System Error (HSE) bit in the USBSTS register.
19:17	-	-	Reserved
16	0b	RO	SMI on Event Interrupt (SMIEI) Default = ‘0’. Shadow bit of Event Interrupt (EINT) bit in the USBSTS register. This bit follows the state the Event Interrupt (EINT) bit in the USBSTS register, e.g. it automatically clears when EINT clears or set when EINT is set.
15	0b	RW	SMI on BAR Enable (SMIBARE) Default = ‘0’. When this bit is ‘1’ and SMI on BAR is ‘1’, then the host controller will issue an SMI.
14	0b	RW	SMI on PCI Command Enable (SMIPCICE) . Default = ‘0’. When this bit is ‘1’ and SMI on PCI Command is ‘1’, then the host controller will issue an SMI.
13	0b	RW	SMI on OS Ownership Enable (SMIOSOE) Default = ‘0’. When this bit is a ‘1’ AND the OS Ownership Change bit is ‘1’, the host controller will issue an SMI.
12:5	-	-	Reserved
4	0b	RW	SMI on Host System Error Enable (SMIHSEE) Default = ‘0’. When this bit is a ‘1’, and the SMI on Host System Error bit (below) in this register is a ‘1’, the host controller will issue an SMI immediately.
3:1	-	-	Reserved
0	0b	RW	USB SMI Enable (USBSMIE) . Default = ‘0’. When this bit is a ‘1’, and the SMI on Event Interrupt bit (below) in this register is a ‘1’, the host controller will issue an SMI immediately.