Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Power Management Capabilities (CNVI_WIFI_PMC) – Offset c8
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:27 | 0x19 | RO | PME_SUPRT (PME_SUPRT) PME Support,indicates the power states in which the device may assert PME |
26 | 0x0 | RO | D2_PWR_MANG (D2_PWR_MANG) D2 Power Management State support |
25 | 0x0 | RO | D1_PWR_MANG (D1_PWR_MANG) D1 Power Management State support |
24:22 | 0x0 | RO | AUX_CUR (AUX_CUR) AUX Current (Used data register instead) |
21 | 0x1 | RO | DEV_SPC_INT (DEV_SPC_INT) Device Specific Initialization |
20 | - | - | Reserved
|
19 | 0x0 | RO | PME_CLK (PME_CLK) Does not apply. Hardwired to 0. |
18:16 | 0x3 | RO | VERSION (VERSION) value indicates that this function complies with the Revision 1.2 |
15:8 | 0xd0 | RO | PMC_NXT_PTR (PMC_NXT_PTR) Next PTR, pointing to the location of next item in the functions capability list HARDWIRED |
7:0 | 0x1 | RO | PMC_CAP_ID (PMC_CAP_ID) Capability ID, Indicates the linked list item is the PCI Power Management Registers HARDWIRED |