Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Device Idle D0i3 (reg_D0i3) – Offset 81c
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:5 | - | - | Reserved
|
4 | 0h | RO | Interrupt Request Capable (Interrupt_Request_Capable) 0 – HW not capable to issue in interrupt on command completion |
3 | 1h | RW/1C | Restore Required (RestoreRequired) When set (by HW), SW must restore state to the IP. The state may have been lost due to a reset or full power lost. SW clears the bit by writing a 1. This bit will be set on initial power up. |
2 | 0h | RW | D0i3 (D0i3) SW sets this bit to 1 to move the IP into the D0i3 state. Writing this bit to 0 will return the IP to the fully active D0 state (D0i0). |
1 | - | - | Reserved
|
0 | 0h | RO | Command In Progress (Cmd_In_Progress) HW sets this bit on a 1->0 or 0->1 transition of bit [2]. While set, the other bits in this register are not valid and it is illegal for SW to write to any bit in this register. |