Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Device Control (DEVC) – Offset 78
NSNPEN bit is not affected by D3HOT to D0 reset or FLR.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15 | 0b | WO | Initiate FLR (IF) Used to initiate FLR transition. A write of 1 initiates FLR transition. |
14:12 | 010b | RW | Max Read Request Size (MRRS) This field sets the maximum Read Request size for the Function as a Requester. The Function must not generate Read Requests with size exceeding the set value. Defined encodings for this field are: |
11 | 1b | RW | Enable No Snoop (NSNPEN) When set to 1 (or EM2.FNSNPEN = 1) the Intel HD Audio controller is |
10 | 0b | RO | Auxiliary (AUX) Power PM Enable (AUXPEN) Hardwired to 0 indicating Intel HD Audio device does not draw AUX power. |
9 | 0b | RO | Phantom Functions Enable (PFEN) Hardwired to 0 disabling phantom functions. |
8 | 0b | RO | Extended Tag Field Enable (ETEN) Hardwired to 0 enabling 5-bit tag. |
7:5 | 000b | RO | Max Payload Size (MAXPAY) Hardwired to 000 indicating 128 B. |
4 | 0b | RO | Enable Relaxed Ordering (ROEN) Hardwired to 0 disabling relaxed ordering. |
3 | 0b | RW | Unsupported Request Reporting Enable (URREN) Functionality not implemented. This bit is R/W to pass PCIe compliance testing. |
2 | 0b | RW | Fatal Error Reporting Enable (FEREN) Functionality not implemented. This bit is R/W to pass PCIe compliance testing. |
1 | 0b | RW | Non-Fatal Error Reporting Enable (NFEREN) Functionality not implemented. This bit is R/W to pass PCIe compliance testing. |
0 | 0b | RW | Correctable Error Reporting Enable (CEREN) Functionality not implemented. This bit is R/W to pass PCIe compliance testing. |