Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
I2C Target Address (IC_TAR) – Offset 4
The register should only be updated when the I2C is not enabled (IC_ENABLE=0) or No Master mode operations are active (IC_STATUS[5] = 0 and IC_CON[0] = 1 and IC_STATUS[2] = 1).
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:13 | - | - | Reserved
|
12 | 1h | RW | 7_10 Bit Adressing (IC_10BITADDR_MASTER) This bit controls whether the I2C starts its transfers in 7-or 10-bit addressing mode when acting as a master. |
11 | 0h | RW | Special (SPECIAL) This bit indicates whether software performs a General Call or START BYTE command. |
10 | 0h | RW | General Call Or START (GC_OR_START) If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the I2C. |
9:0 | 55h | RW | Target Address (IC_TAR) This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. |