General PM Configuration B (GEN_PMCON_B) – Offset 1024 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

General PM Configuration B (GEN_PMCON_B) – Offset 1024

Bit Range	Default	Access	Field Name and Description
30:19	-	-	Reserved
18	0b	RW/L	SLP_Sx# Stretching Policy Lock-Down (SLPSX_STR_POL_LOCK) When set to 1, this bit locks down the following fields: - GEN_PMCON.DIS_SLP_X_STRCH_SUSPF - GEN_PMCON.SLP_S3_MIN_ASST_WDTH - GEN_PMCON.S4MAW - GEN_PMCON.S4ASE - PM_CFG.SLP_A_MIN_ASST_WDTH - PM_CFG.SLP_LAN_MIN_ASST_WDTH - PM_CFG.PWR_CYC_DUR Those bits become read-only. This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit are always ignored. Once locked by writing 1, the only way to clear this bit is to perform a platform reset. This lockdown bit is available in both desktop and mobile.
17	-	-	Reserved
16	0b	RW/L	PM_DATA_BAR Disable (PM_DATA_BAR_DIS) When set t0 1, this bit disables all accesses to the MMip range pointed to by the PM_DATA_BAR. THis does not affect the BAR value itself, which can still be changed after this bit is set. But once this bit is set, PMC will drop writes to the data region pointed to by PM_DATA_BAR and reads will return 0. This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit are always ignored. Once locked by writing 1, the only way to clear this bit is to perform a platform reset.
15:14	-	-	Reserved
13	0b	RW	WOL Enable Override (WOL_EN_OVRD) When this bit is set to 1, the integrated LAN is enabled to wake the system from S5 regardless of the value in the PME_B0_EN bit in the GPE0_EN register. This allows the system BIOS to enable Wake-On-LAN regardless of the policies selected through the operating system. This bit is maintained in the RTC power well, therefore permitting WOL following a surprise power failure even in cases in which the system may have been running in S0 without the PME Enables set. (Note that the LAN NVRAM configuration must support WOL after SUS power loss.) When this bit is cleared to 0, the wake-on-LAN policies are determined by OS-visible bits. This bit has no effect on wakes from S1, S3, or S4. This bit is cleared by the RTCRST# pin
12:11	-	-	Reserved
10	0b	RW	BIOS PCI Express Enable (BIOS_PCI_EXP_EN) This bit acts as a global enable for the SCI associated with the PCI express ports. If this bit is not set, then the various PCI Express ports cannot cause the PCI_EXP_STS bit to go active.
9	0b	RO/V	Power Button Level (PWRBTN_LVL) This read-only bit indicates the current state of the PWRBTN# signal. 1= High, 0 = Low. The value reflected in this bit is dependent upon PM_CFG1.PB_DB_MODE. The PB_DB_MODE bit's value causes the following behavior: - '0': PWRBTN_LVL is taken from the debounced PWRBTN# pin value that is seen at the output of a 16ms debouncer. - '1': PWRBTN_LVL is taken from the raw PWRBTN# pin (before the debouncer).
8:5	-	-	Reserved
4	0b	RW/L	SMI Lock (SMI_LOCK) When this bit is set, writes to the GLB_SMI_EN bit will have no effect. Once the SMI_LOCK bit is set, writes of 0 to SMI_LOCK bit will have no effect (i.e. once set, this bit can only be cleared by RSMRST#).
3	-	-	Reserved
2	1b	RW	RTC_PWR_STS (RPS) The PCH will set this bit to 1 when RTCRST# indicates a weak or missing battery. The bit will remain set until the software clears it by writing a 0 back to this bit position. This bit is not cleared by any type of reset.
1:0	-	-	Reserved