Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Device Status (STS) – Offset 6
Device Status
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15 | 0h | RW/1C/V | Detected Parity Error (DPE) 0 = No parity error detected by SATA controller. |
14 | 0h | RW/1C/V | Signalled System Error (SSE) 0 = No SERR# detected by SATA controller. |
13 | 0h | RW/1C/V | Received Master-Abort Status (RMA) 0 = Master abort not generated. |
12 | 0h | RW/1C/V | Received Target-Abort Status (RTA) 0 = Target abort not generated. |
11 | 0h | RW/1C/V | Signalled Target-Abort Status (STA) This bit must be set by a target device whenever it terminates a transaction with Target-Abort. Devices that will never signal Target-Abort do not need to implement this bit. |
10:9 | 1h | RO | DEVSEL# Timing Status (DEVT) 01 = Hardwired; Controls the device select time for the SATA controller’s PCI interface. |
8 | 0h | RW/1C/V | Master Data Parity Error Detected (DPD) For PCH, this bit can only be set on read completions received from the bus when there is a parity error. |
7:5 | - | - | Reserved
|
4 | 1h | RO | Capabilities List (CL) Indicates the presence of a capabilities list. The minimum requirement for the capabilities list must be PCI power management for the SATA Controller. |
3 | 0h | RO/V | Interrupt Status (IS) Reflects the state of INTx# messages, IRQ14 or IRQ15. |
2:0 | - | - | Reserved
|