Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Normal Interrupt Status Enable (normalintrstsena) – Offset 34
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
14 | 0h | RO | Boot terminate Interrupt Enable (Boot_Term_Int) This status is set if the boot operation gets terminated. |
13 | 0h | RW | Boot ack rcv enable (FX_event_sts_enb) This status is set if the boot acknowledge is received from device. |
12 | 0h | RW | Re-Tuning Event Status Enable (re_tuning_evnt_sts_enb) This status is set if Re-Tuning Request in the Present State register changes from 0 to 1. |
11 | 0h | RW | INT_C Status Enable (int_c_sts_enb) If this bit is set to 0, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent inadvertent interrupts |
10 | 0h | RW | INT_B Status Enable (int_b_sts_enb) If this bit is set to 0, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and mayset this bit again after all interrupt requests to INT_B pin are cleared to prevent inadvertent interrupts |
9 | 0h | RW | INT_A Status Enable (int_a_sts_enb) If this bit is set to 0, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent inadvertent interrupts |
8 | 0h | RW | Card Interrupt Status Enable (sdhcregset_cardintstsena) If this bit is set to 0, the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The HD may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all Interrupt requests from the card are cleared to prevent inadvertent Interrupts. |
7 | 0h | RW | Card Removal Status Enable (sdhcregset_cardremstsena) This status is set if the Card Inserted in the Present State register changes from 1 to 0. |
6 | 0h | RW | Card Insertion Status Enable (sdhcregset_cardinsstsena) This status is set if the Card Inserted in the Present State register changes from 0 to 1. |
5 | 0h | RW | Buffer Read Ready Status Enable (buffer_rd_ready_sts_en) This status is set if the Buffer Read Enable changes from 0 to 1. |
4 | 0h | RW | Buffer Write Ready Status Enable (buffer_wr_ready_sts_en) This status is set if the Buffer Write Enable changes from 0 to 1. |
3 | 0h | RW | DMA Interrupt Status Enable (dma_intr_sts_enb) This status is set if the HC detects the Host DMA Buffer Boundary in the Block Size register. |
2 | 0h | RW | Block Gap Event Status Enable (block_gap_event_sts_enb) If the Stop At Block Gap Request in the BlockGap Control Register is set, this bit is set. |
1 | 0h | RW | Transfer Complete Status Enable (transfer_complete_sts_enb) This bit is set when a read / write transaction is completed. |
0 | 0h | RW | Command Complete Status Enable (cmd_complete_sts_enb) This bit is set when we get the end bit of the command response. |